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envelope-from=bin.meng@processmission.com; helo=TYDPR03CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Instantiate the E2000 DDR controller device and map it over the board-control placeholder. PBF and early U-Boot poll this selector window while firmware coordinates DRAM initialization from EL3. Signed-off-by: Bin Meng --- Changes in v2: - Move the DDR status device into the E2000 SoC hw/arm/phytium_e2000.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/hw/arm/phytium_e2000.c b/hw/arm/phytium_e2000.c index da8313d61f..9a0cc00c91 100644 --- a/hw/arm/phytium_e2000.c +++ b/hw/arm/phytium_e2000.c @@ -21,6 +21,7 @@ #include "hw/core/qdev-properties.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_its_common.h" +#include "hw/misc/phytium_e2000_ddr.h" #include "hw/misc/unimp.h" #include "hw/net/cadence_gem.h" #include "hw/pci/pci.h" @@ -39,6 +40,8 @@ #define PHYTIUM_E2000_NUM_UARTS 7 +#define PHYTIUM_E2000_DDR_STATUS_BASE 0x32b33000 + #define PHYTIUM_E2000_GTIMER_HZ 50000000 /* @@ -462,6 +465,21 @@ static void phytium_e2000_create_mci(PhytiumE2000SoCState *s, int index) qdev_get_gpio_in(s->gic, phytium_e2000_mci_irqmap[index])); } +static void phytium_e2000_create_ddr_status(PhytiumE2000SoCState *s) +{ + DeviceState *dev = qdev_new(TYPE_PHYTIUM_E2000_DDR); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + /* + * The selector window is embedded in the board-control aperture. It must + * override the placeholder because early U-Boot polls it while PBF is + * still coordinating DRAM initialization from EL3. + */ + object_property_add_child(OBJECT(s), "ddr-status", OBJECT(dev)); + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map_overlap(sbd, 0, PHYTIUM_E2000_DDR_STATUS_BASE, 2); +} + static void phytium_e2000_create_unimplemented(PhytiumE2000SoCState *s) { /* @@ -584,6 +602,8 @@ static void phytium_e2000_soc_realize(DeviceState *dev, Error **errp) phytium_e2000_create_cpus(s); phytium_e2000_create_gic(s); + phytium_e2000_create_ddr_status(s); + for (i = 0; i < PHYTIUM_E2000_NUM_MCIS; i++) { phytium_e2000_create_mci(s, i); } -- 2.53.0