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envelope-from=bin.meng@processmission.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Instantiate QSPI0 at its command and direct-map windows so accesses from E2000 firmware reach the controller model. Signed-off-by: Bin Meng --- Changes in v2: - Move the QSPI controller into the E2000 SoC - Store the QSPI child with its concrete QOM state type include/hw/arm/phytium_e2000.h | 4 ++++ hw/arm/phytium_e2000.c | 15 +++++++++++++++ hw/arm/Kconfig | 1 + 3 files changed, 20 insertions(+) diff --git a/include/hw/arm/phytium_e2000.h b/include/hw/arm/phytium_e2000.h index 40f91256a2..92b39129ba 100644 --- a/include/hw/arm/phytium_e2000.h +++ b/include/hw/arm/phytium_e2000.h @@ -16,6 +16,7 @@ #include "hw/core/sysbus.h" #include "hw/net/cadence_gem.h" #include "hw/sd/phytium_e2000_mci.h" +#include "hw/ssi/phytium_qspi.h" #include "qemu/typedefs.h" #include "target/arm/cpu.h" @@ -27,9 +28,11 @@ OBJECT_DECLARE_SIMPLE_TYPE(PhytiumE2000SoCState, PHYTIUM_E2000_SOC) #define PHYTIUM_E2000_NUM_GEMS 4 enum { + PHYTIUM_E2000_QSPI_DIRECT, PHYTIUM_E2000_LOW_PERIPH, PHYTIUM_E2000_MCI0, PHYTIUM_E2000_MCI1, + PHYTIUM_E2000_QSPI_REGS, PHYTIUM_E2000_UART0, PHYTIUM_E2000_UART1, PHYTIUM_E2000_UART2, @@ -63,6 +66,7 @@ struct PhytiumE2000SoCState { SysBusDevice parent_obj; DeviceState *gic; + PhytiumE2000QSPIState *qspi; PhytiumE2000MciState *mci[PHYTIUM_E2000_NUM_MCIS]; CadenceGEMState *gem[PHYTIUM_E2000_NUM_GEMS]; ARMCPU cpu[PHYTIUM_E2000_NUM_CPUS]; diff --git a/hw/arm/phytium_e2000.c b/hw/arm/phytium_e2000.c index 95ebf3c87b..3e30d112f7 100644 --- a/hw/arm/phytium_e2000.c +++ b/hw/arm/phytium_e2000.c @@ -28,6 +28,7 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" #include "hw/sd/sd.h" +#include "hw/ssi/phytium_qspi.h" #include "net/net.h" #include "qobject/qlist.h" #include "qom/object.h" @@ -54,9 +55,11 @@ * handoff data and IACC is the fixed execution window for system firmware. */ const MemMapEntry phytium_e2000_memmap[] = { + [PHYTIUM_E2000_QSPI_DIRECT] = { 0x00000000, 0x10000000 }, [PHYTIUM_E2000_LOW_PERIPH] = { 0x28000000, 0x00100000 }, [PHYTIUM_E2000_MCI0] = { 0x28000000, 0x00001000 }, [PHYTIUM_E2000_MCI1] = { 0x28001000, 0x00001000 }, + [PHYTIUM_E2000_QSPI_REGS] = { 0x28008000, 0x00001000 }, [PHYTIUM_E2000_UART0] = { 0x2800c000, 0x00001000 }, [PHYTIUM_E2000_UART1] = { 0x2800d000, 0x00001000 }, [PHYTIUM_E2000_UART2] = { 0x2800e000, 0x00001000 }, @@ -469,6 +472,17 @@ static void phytium_e2000_create_mci(PhytiumE2000SoCState *s, int index) qdev_get_gpio_in(s->gic, phytium_e2000_mci_irqmap[index])); } +static void phytium_e2000_create_qspi(PhytiumE2000SoCState *s) +{ + s->qspi = PHYTIUM_E2000_QSPI(qdev_new(TYPE_PHYTIUM_E2000_QSPI)); + object_property_add_child(OBJECT(s), "qspi", OBJECT(s->qspi)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(s->qspi), &error_fatal); + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->qspi), 0, + phytium_e2000_memmap[PHYTIUM_E2000_QSPI_REGS].base, 2); + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->qspi), 1, + phytium_e2000_memmap[PHYTIUM_E2000_QSPI_DIRECT].base, 2); +} + static void phytium_e2000_create_ddr_status(PhytiumE2000SoCState *s) { DeviceState *dev = qdev_new(TYPE_PHYTIUM_E2000_DDR); @@ -631,6 +645,7 @@ static void phytium_e2000_soc_realize(DeviceState *dev, Error **errp) } phytium_e2000_create_unimplemented(s); + phytium_e2000_create_qspi(s); phytium_e2000_create_cpus(s); phytium_e2000_create_gic(s); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index d9759731f0..e4111eaec2 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -136,6 +136,7 @@ config PHYTIUM_E2000 select DW_MCI select PCI_EXPRESS select PCI_EXPRESS_GENERIC_BRIDGE + select PHYTIUM_E2000_QSPI select PL011 select SD select UNIMP -- 2.53.0