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envelope-from=david.vrabel@nutanix.com; helo=mx0b-002c1b01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org For guests with passthrough PCIe devices, in order to make the guest=0A= PCIe topology have the same apparent bandwidth as the underlying=0A= hardware we need to be able to set the capabilities (speed and width)=0A= of the virtual root, upstream, and downstream ports.=0A= =0A= Promote the existing experimental `x-speed` and `x-width` options to=0A= non-experimental `speed` and `width`.=0A= =0A= Signed-off-by: David Vrabel =0A= ---=0A= hw/pci-bridge/gen_pcie_downstream_port.c | 4 ++--=0A= hw/pci-bridge/gen_pcie_root_port.c | 4 ++--=0A= hw/pci-bridge/gen_pcie_upstream_port.c | 4 ++--=0A= 3 files changed, 6 insertions(+), 6 deletions(-)=0A= =0A= diff --git a/hw/pci-bridge/gen_pcie_downstream_port.c b/hw/pci-bridge/gen_p= cie_downstream_port.c=0A= index d593846ac1..8fe71382aa 100644=0A= --- a/hw/pci-bridge/gen_pcie_downstream_port.c=0A= +++ b/hw/pci-bridge/gen_pcie_downstream_port.c=0A= @@ -163,9 +163,9 @@ static const VMStateDescription vmstate_gen_pcie_downst= ream_port =3D {=0A= static const Property gen_pcie_downstream_port_props[] =3D {=0A= DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,=0A= QEMU_PCIE_SLTCAP_PCP_BITNR, true),=0A= - DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,=0A= + DEFINE_PROP_PCIE_LINK_SPEED("speed", PCIESlot,=0A= speed, PCIE_LINK_SPEED_64),=0A= - DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,=0A= + DEFINE_PROP_PCIE_LINK_WIDTH("width", PCIESlot,=0A= width, PCIE_LINK_WIDTH_32),=0A= };=0A= =0A= diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c=0A= index 5434d693d9..d3ace7f0db 100644=0A= --- a/hw/pci-bridge/gen_pcie_root_port.c=0A= +++ b/hw/pci-bridge/gen_pcie_root_port.c=0A= @@ -129,9 +129,9 @@ static const Property gen_rp_props[] =3D {=0A= res_reserve.mem_pref_32, -1),=0A= DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,=0A= res_reserve.mem_pref_64, -1),=0A= - DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,=0A= + DEFINE_PROP_PCIE_LINK_SPEED("speed", PCIESlot,=0A= speed, PCIE_LINK_SPEED_16),=0A= - DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,=0A= + DEFINE_PROP_PCIE_LINK_WIDTH("width", PCIESlot,=0A= width, PCIE_LINK_WIDTH_32),=0A= };=0A= =0A= diff --git a/hw/pci-bridge/gen_pcie_upstream_port.c b/hw/pci-bridge/gen_pci= e_upstream_port.c=0A= index 57d7e09485..edd5bfcafc 100644=0A= --- a/hw/pci-bridge/gen_pcie_upstream_port.c=0A= +++ b/hw/pci-bridge/gen_pcie_upstream_port.c=0A= @@ -139,9 +139,9 @@ static const VMStateDescription vmstate_gen_pcie_upstre= am_port =3D {=0A= };=0A= =0A= static const Property gen_pcie_upstream_port_props[] =3D {=0A= - DEFINE_PROP_PCIE_LINK_SPEED("x-speed", GenPCIEUpstreamPort,=0A= + DEFINE_PROP_PCIE_LINK_SPEED("speed", GenPCIEUpstreamPort,=0A= speed, PCIE_LINK_SPEED_64),=0A= - DEFINE_PROP_PCIE_LINK_WIDTH("x-width", GenPCIEUpstreamPort,=0A= + DEFINE_PROP_PCIE_LINK_WIDTH("width", GenPCIEUpstreamPort,=0A= width, PCIE_LINK_WIDTH_32),=0A= };=0A= =0A= -- =0A= 2.43.0=0A= =0A=