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Tsirkin" , Zhao Liu , Paolo Bonzini Subject: [PATCH v2 3/4] hw/pci-bridge: Default the generic PCIe root port as Gen6 capable Thread-Topic: [PATCH v2 3/4] hw/pci-bridge: Default the generic PCIe root port as Gen6 capable Thread-Index: AQHdP6oL9O9Mw2/ps0m1xjmZ4zrXdQ== Date: Tue, 8 Sep 2026 15:52:26 +0000 Message-ID: <20260908155223.164787-4-david.vrabel@nutanix.com> References: <20260908155223.164787-1-david.vrabel@nutanix.com> In-Reply-To: <20260908155223.164787-1-david.vrabel@nutanix.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SA1PR02MB8368:EE_|BN0PR02MB8064:EE_ x-ms-office365-filtering-correlation-id: dbe985c4-3b62-4a9d-3185-08df0dc12e5a x-proofpoint-crosstenant: true x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|366016|376014|23010399003|1800799024|6133799003|18002099003|22082099003|38070700021|56012099006|10067099003; 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envelope-from=david.vrabel@nutanix.com; helo=mx0b-002c1b01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org As part of making virtual PCIe topology having the same apparent=0A= bandwidth as a the underlying hardware, make the generic PCIe root=0A= port support maximum speed so by default it doesn't appear to be a=0A= bottleneck.=0A= =0A= This also makes the three generic PCIe ports (root, upstream, and=0A= downstream) have the same link speed/width capabilities.=0A= =0A= Signed-off-by: David Vrabel =0A= ---=0A= hw/pci-bridge/gen_pcie_root_port.c | 2 +-=0A= 1 file changed, 1 insertion(+), 1 deletion(-)=0A= =0A= diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c=0A= index d3ace7f0db..8cabeadac8 100644=0A= --- a/hw/pci-bridge/gen_pcie_root_port.c=0A= +++ b/hw/pci-bridge/gen_pcie_root_port.c=0A= @@ -130,7 +130,7 @@ static const Property gen_rp_props[] =3D {=0A= DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,=0A= res_reserve.mem_pref_64, -1),=0A= DEFINE_PROP_PCIE_LINK_SPEED("speed", PCIESlot,=0A= - speed, PCIE_LINK_SPEED_16),=0A= + speed, PCIE_LINK_SPEED_64),=0A= DEFINE_PROP_PCIE_LINK_WIDTH("width", PCIESlot,=0A= width, PCIE_LINK_WIDTH_32),=0A= };=0A= -- =0A= 2.43.0=0A= =0A=