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envelope-from=david.vrabel@nutanix.com; helo=mx0b-002c1b01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org If an emulated PCIe endpoint has higher link speed or width=0A= capabilities than the upstream port it is connected to, ensure that=0A= the link status on both ends is consistent by using the link status=0A= computed for the upstream port.=0A= =0A= If the PCIe endpoint is a passthrough device, the link status=0A= continues to match the real status and consistent values requires the=0A= emulated upstream port to be at least as capable as the endpoint.=0A= =0A= Signed-off-by: David Vrabel =0A= ---=0A= hw/pci/pcie.c | 26 ++++++++++++++++++++++----=0A= 1 file changed, 22 insertions(+), 4 deletions(-)=0A= =0A= diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c=0A= index 4622c75e48..66d778413d 100644=0A= --- a/hw/pci/pcie.c=0A= +++ b/hw/pci/pcie.c=0A= @@ -169,18 +169,36 @@ void pcie_cap_fill_link_ep_usp(PCIDevice *dev, PCIExp= LinkWidth width,=0A= PCIExpLinkSpeed speed, bool flitmode)=0A= {=0A= uint8_t *exp_cap =3D dev->config + dev->exp.exp_cap;=0A= + PCIDevice *upstream;=0A= =0A= /*=0A= - * For an end point or USP need to set the current status as well=0A= - * as the capabilities.=0A= + * For an endpoint or USP, set Link Status as well as capabilities.=0A= + * Provisionally use this device's width/speed, then adopt the upstrea= m=0A= + * port's values so both ends of an emulated link agree. The upstream= =0A= + * LNKSTA is already clamped to the negotiated link capabilities via= =0A= + * pcie_sync_bridge_lnk().=0A= */=0A= - pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,=0A= + pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,=0A= PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW);= =0A= - pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,=0A= + pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,=0A= QEMU_PCI_EXP_LNKSTA_NLW(width) |=0A= QEMU_PCI_EXP_LNKSTA_CLS(speed));=0A= =0A= pcie_cap_fill_lnk(exp_cap, width, speed, flitmode);=0A= +=0A= + upstream =3D pci_bridge_get_device(pci_get_bus(dev));=0A= + if (upstream && pci_is_express_downstream_port(upstream)) {=0A= + uint8_t *up_exp =3D upstream->config + upstream->exp.exp_cap;=0A= + uint16_t lnksta;=0A= +=0A= + pcie_sync_bridge_lnk(upstream);=0A= + lnksta =3D pci_get_word(up_exp + PCI_EXP_LNKSTA);=0A= + pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,=0A= + PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_N= LW);=0A= + pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,=0A= + lnksta & (PCI_EXP_LNKSTA_CLS |=0A= + PCI_EXP_LNKSTA_NLW));=0A= + }=0A= }=0A= =0A= static void pcie_cap_fill_slot_lnk(PCIDevice *dev)=0A= -- =0A= 2.43.0=0A= =0A=