From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB955342CB0 for ; Tue, 8 Sep 2026 16:01:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788883291; cv=none; b=EGbfvfgeiyPuXkVReM1rZfak8mn1gV/JeBWQSz67zDxjl3lID/zo6RuYCmUl6sHBdKUdZ+4Q11RRpi7A4PM6wROf4gnkkjXMHg7aL2x/PEkMQrLIxPgvr5ZWjP7rUT968yc33C6WOZupx15SCaCO4htBpg75Hl0x+qwrJmlX7rI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788883291; c=relaxed/simple; bh=YzxZGtQb9i5Ggvvf1NJK2w78guD8itBCrtEKzLOZy60=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CTO3Sj+QcdmgRwYJvnRr7zhu4wB5Xf/5X8OwJih5Jw+5acS7c6S8U1PYpuUCreIwRjHcpvlPEw9O6ygrsk6B3rn9AHeapmWqooZI0tluH4rWwCKpnmwvfcGtmlh75Z+czYTsQdSvV/nEQOWbAlDEYURldAyywtk34hy4xOSyIMI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RSg9H+B4; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RSg9H+B4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A191D1F00A3A; Tue, 8 Sep 2026 16:01:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788883289; bh=y+uw9D7lq4NVE4rl5+TQJ5568hnTQUmlk7oK5ei7LB8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=RSg9H+B49H5ElHhkzAlZeB8h9/R1cAs/J4dwtMsNl2Z1a9Pm+IJJrntDvQwo/GXbV oBMSf1oLMHoIeOnOORHB2/MtDqNyE7VmPe7tQIJxdCmzkdEeYcbha4KO6eIAllg5Qt 34f+jvUxxJyTP49Lsiml7Ob8+0DfhxtA7650VHmh473pGuPWH1WIjXE1AL2E8/YxnA gsYn/f3y1CaDLTXs2DmBqyUsTfLNfaW9PKu2VPvbNSvPWOHZnXI9JWyRcL6WcMzrya gHCZ489VAGmR0Mcq5yAagg1UDNoE3JJ3wjbJ3gS1AvoYdfMc90TFiEk0XLd+FthwC2 ALwB1yE76Gf6w== From: Sasha Levin To: stable@vger.kernel.org Cc: Terry Bowman , Kuppuswamy Sathyanarayanan , Jonathan Cameron , Dave Jiang , Joshua Hahn , Dan Williams , Sasha Levin Subject: [PATCH 6.12.y 1/4] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Date: Tue, 8 Sep 2026 12:01:24 -0400 Message-ID: <20260908160127.2548313-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026090317-roundish-company-df16@gregkh> References: <2026090317-roundish-company-df16@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Terry Bowman [ Upstream commit ca3d1a53e62093d17436abd447463da9c0f4e56b ] The CXL driver's cxl_handle_endpoint_cor_ras()/cxl_handle_endpoint_ras() are unnecessary helper functions used only for Endpoints. Remove these functions as they are not common for all CXL devices and do not provide value for EP handling. Rename __cxl_handle_ras to cxl_handle_ras() and __cxl_handle_cor_ras() to cxl_handle_cor_ras(). Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Tested-by: Joshua Hahn Reviewed-by: Dan Williams Link: https://patch.msgid.link/20260114182055.46029-5-terry.bowman@amd.com Signed-off-by: Dan Williams Signed-off-by: Dave Jiang Stable-dep-of: 9d399526128b ("cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity register") Signed-off-by: Sasha Levin --- drivers/cxl/core/pci.c | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 5b46bc46aaa95..c70b75a6f6fe5 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -650,8 +650,8 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL); -static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) +static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, + void __iomem *ras_base) { void __iomem *addr; u32 status; @@ -667,11 +667,6 @@ static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, } } -static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras); -} - /* CXL spec rev3.0 8.2.4.16.1 */ static void header_log_copy(void __iomem *ras_base, u32 *log) { @@ -693,8 +688,8 @@ static void header_log_copy(void __iomem *ras_base, u32 *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) +static bool cxl_handle_ras(struct cxl_dev_state *cxlds, + void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -727,11 +722,6 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, return true; } -static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_ras(cxlds, cxlds->regs.ras); -} - #ifdef CONFIG_PCIEAER_CXL static void cxl_dport_map_rch_aer(struct cxl_dport *dport) @@ -810,13 +800,13 @@ EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, CXL); static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_cor_ras(cxlds, dport->regs.ras); + return cxl_handle_cor_ras(cxlds, dport->regs.ras); } static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_ras(cxlds, dport->regs.ras); + return cxl_handle_ras(cxlds, dport->regs.ras); } /* @@ -913,7 +903,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev) if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); - cxl_handle_endpoint_cor_ras(cxlds); + cxl_handle_cor_ras(cxlds, cxlds->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, CXL); @@ -942,7 +932,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue = cxl_handle_endpoint_ras(cxlds); + ue = cxl_handle_ras(cxlds, cxlds->regs.ras); } -- 2.53.0