From: Sasha Levin <sashal@kernel.org>
To: stable@vger.kernel.org
Cc: Terry Bowman <terry.bowman@amd.com>,
Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>,
Dave Jiang <dave.jiang@intel.com>,
Richard Cheng <icheng@nvidia.com>,
Alison Schofield <alison.schofield@intel.com>,
Sasha Levin <sashal@kernel.org>
Subject: [PATCH 6.12.y 4/4] cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity register
Date: Tue, 8 Sep 2026 12:01:27 -0400 [thread overview]
Message-ID: <20260908160127.2548313-4-sashal@kernel.org> (raw)
In-Reply-To: <20260908160127.2548313-1-sashal@kernel.org>
From: Terry Bowman <terry.bowman@amd.com>
[ Upstream commit 9d399526128bae184b153deab42b49f5f3eea2ed ]
cxl_rch_get_aer_severity() classifies RCH Downstream Port uncorrectable
errors as fatal or non-fatal by ANDing uncorrectable status with
PCI_ERR_ROOT_FATAL_RCV. This is wrong because PCI_ERR_ROOT_FATAL_RCV is a
Root Error Status register bit (bit 6), not a severity bit. ANDing it
against uncorrectable status tests a reserved bit and produces incorrect
severity classification.
Fix by ANDing the unmasked uncor_status against uncor_severity. Per
PCIe Base Spec r6.0 Section 7.8.4.4, each bit in the Uncorrectable
Error Severity register indicates whether the corresponding error is
fatal (1) or non-fatal (0).
Fixes: 6ac07883dbb5 ("cxl/pci: Add RCH downstream port error logging")
Cc: stable@vger.kernel.org
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Richard Cheng <icheng@nvidia.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20260803221810.3685703-3-terry.bowman@amd.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/cxl/core/ras_rch.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c
index ed58afd18ecc9..cc70373d97fc5 100644
--- a/drivers/cxl/core/ras_rch.c
+++ b/drivers/cxl/core/ras_rch.c
@@ -79,11 +79,11 @@ static bool cxl_rch_get_aer_info(void __iomem *aer_base,
static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs,
int *severity)
{
- if (aer_regs->uncor_status & ~aer_regs->uncor_mask) {
- if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV)
- *severity = AER_FATAL;
- else
- *severity = AER_NONFATAL;
+ u32 uncor_status = aer_regs->uncor_status & ~aer_regs->uncor_mask;
+
+ if (uncor_status) {
+ *severity = (uncor_status & aer_regs->uncor_severity) ?
+ AER_FATAL : AER_NONFATAL;
return true;
}
--
2.53.0
prev parent reply other threads:[~2026-09-08 16:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 13:54 FAILED: patch "[PATCH] cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity" failed to apply to 6.12-stable tree gregkh
2026-09-08 16:01 ` [PATCH 6.12.y 1/4] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Sasha Levin
2026-09-08 16:01 ` [PATCH 6.12.y 2/4] cxl/pci: Remove unnecessary CXL RCH " Sasha Levin
2026-09-08 16:01 ` [PATCH 6.12.y 3/4] cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.c Sasha Levin
2026-09-08 16:01 ` Sasha Levin [this message]
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