From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
richard.henderson@linaro.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Chao Liu <chao.liu@processmission.com>,
Max Chou <max.chou@sifive.com>
Subject: [PATCH 0/6] tests/tcg/riscv64: Add system mode rvv ld/st tests
Date: Wed, 9 Sep 2026 16:41:47 +0800 [thread overview]
Message-ID: <20260909084154.223529-1-max.chou@sifive.com> (raw)
Hi Richard,
This patchset adds several rvv load/store tests with PMP permission
settings, as we discussed during your v1 submission.
While building the tests, I noticed that pmp_hart_has_privs has a scope
issue that yields unexpected results. This affects both the vector
fault-only-first load and vector unit-stride ld/st instructions.
I therefore attempted to correct pmp_hart_has_privs and
vext_ldst_us_notail, adding matching tests.
Hope these system mode tests and fixes can help you.
PS: I tried applying v2
<20260821040404.268123-1-richard.henderson@linaro.org> to the master and
riscv-to-apply.next branches, but both conflicted.
Thanks,
rnax
Based-on: <20260821040404.268123-1-richard.henderson@linaro.org>
Max Chou (6):
target/riscv: Match PMP entries lying inside the checked range
target/riscv: rvv: Probe unit-stride accesses by the first element
tests/tcg/riscv64: Add vector masked fault-only-first PMP test
tests/tcg/riscv64: Add vector unit-stride PMP test
tests/tcg/riscv64: Add vector fault-only-first page probe test
tests/tcg/riscv64: Add vector segment PMP region spanning test
target/riscv/tcg/pmp.c | 31 +--
target/riscv/tcg/vector_helper.c | 45 +++-
tests/tcg/riscv64/Makefile.softmmu-target | 38 +++
tests/tcg/riscv64/rvv-ldst.inc | 91 +++++++
tests/tcg/riscv64/test-rvv-ldst-ff-page.S | 83 +++++++
tests/tcg/riscv64/test-rvv-ldst-ff-pmp.S | 259 ++++++++++++++++++++
tests/tcg/riscv64/test-rvv-ldst-seg-pmp.S | 141 +++++++++++
tests/tcg/riscv64/test-rvv-ldst-us-pmp.S | 281 ++++++++++++++++++++++
8 files changed, 943 insertions(+), 26 deletions(-)
create mode 100644 tests/tcg/riscv64/rvv-ldst.inc
create mode 100644 tests/tcg/riscv64/test-rvv-ldst-ff-page.S
create mode 100644 tests/tcg/riscv64/test-rvv-ldst-ff-pmp.S
create mode 100644 tests/tcg/riscv64/test-rvv-ldst-seg-pmp.S
create mode 100644 tests/tcg/riscv64/test-rvv-ldst-us-pmp.S
--
2.43.0
next reply other threads:[~2026-09-09 8:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-09 8:41 Max Chou [this message]
2026-09-09 8:41 ` [PATCH 1/6] target/riscv: Match PMP entries lying inside the checked range Max Chou
2026-09-09 8:41 ` [PATCH 2/6] target/riscv: rvv: Probe unit-stride accesses by the first element Max Chou
2026-09-09 8:41 ` [PATCH 3/6] tests/tcg/riscv64: Add vector masked fault-only-first PMP test Max Chou
2026-09-11 5:49 ` Chao Liu
2026-09-09 8:41 ` [PATCH 4/6] tests/tcg/riscv64: Add vector unit-stride " Max Chou
2026-09-09 8:41 ` [PATCH 5/6] tests/tcg/riscv64: Add vector fault-only-first page probe test Max Chou
2026-09-09 8:41 ` [PATCH 6/6] tests/tcg/riscv64: Add vector segment PMP region spanning test Max Chou
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