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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2db56c2a1f1sm38328225ad.78.2026.09.09.01.42.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 01:42:41 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Chou Subject: [PATCH 2/6] target/riscv: rvv: Probe unit-stride accesses by the first element Date: Wed, 9 Sep 2026 16:41:49 +0800 Message-ID: <20260909084154.223529-3-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260909084154.223529-1-max.chou@sifive.com> References: <20260909084154.223529-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=max.chou@sifive.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Probe only the first access of the range with probe_access_full and inspect the resulting lg_page_size: when the page is subdivided, fall back to the per-element TLB path. Pages with uniform permissions keep the direct host fast path. Signed-off-by: Max Chou --- target/riscv/tcg/vector_helper.c | 45 ++++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 5 deletions(-) diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c index efe10156daa..569da995482 100644 --- a/target/riscv/tcg/vector_helper.c +++ b/target/riscv/tcg/vector_helper.c @@ -406,6 +406,41 @@ static void vext_test_alignment(CPURISCVState *env, vaddr addr, uint32_t esz, } } +static void *vext_probe_host_page(CPURISCVState *env, target_ulong addr, + target_ulong probe_bytes, uint32_t msize, + MMUAccessType access_type, int mmu_index, + uintptr_t ra) +{ +#ifdef CONFIG_USER_ONLY + return probe_access(env, addr, probe_bytes, access_type, mmu_index, ra); +#else + CPUTLBEntryFull *full; + void *host; + int flags; + + flags = probe_access_full(env, addr, MIN(msize, probe_bytes), + access_type, mmu_index, false, &host, &full, ra); + if (flags || full->lg_page_size < TARGET_PAGE_BITS) { + return NULL; + } + + if (access_type == MMU_DATA_STORE) { + /* + * The permissions are uniform across the page, so probing the + * first access has validated the whole range. It has only + * marked MIN(msize, probe_bytes) bytes as dirty, though, while + * the caller writes probe_bytes through the returned host + * pointer. Probe the whole range as well, so that + * notdirty_write invalidates every translation block that it + * overlaps and the migration dirty bitmap covers all of it. + */ + return probe_access(env, addr, probe_bytes, access_type, + mmu_index, ra); + } + return host; +#endif +} + static void vext_ldst_us_notail(void *vd, target_ulong base, CPURISCVState *env, uint32_t log2_esz, uint32_t nf, uint32_t evl, @@ -448,9 +483,9 @@ vext_ldst_us_notail(void *vd, target_ulong base, CPURISCVState *env, page_split = -(addr | TARGET_PAGE_MASK); /* Validate the first page is accessible. */ - host = probe_access(env, adjust_addr(env, addr), - MIN(last, last_in_page) - addr + 1, - access_type, mmu_index, ra); + host = vext_probe_host_page(env, adjust_addr(env, addr), + MIN(last, last_in_page) - addr + 1, + msize, access_type, mmu_index, ra); /* Get number of complete elements in the first page. */ elems = MIN(page_split / msize, evl - i); @@ -490,8 +525,8 @@ vext_ldst_us_notail(void *vd, target_ulong base, CPURISCVState *env, /* Validate the second page is accessible. */ assert(i < evl); elems = evl - i; - host = probe_access(env, adjust_addr(env, addr), elems * msize, - access_type, mmu_index, ra); + host = vext_probe_host_page(env, adjust_addr(env, addr), elems * msize, + msize, access_type, mmu_index, ra); if (host) { vext_page_ldst_us_host(vd, host, i, evl, nf, log2_esz, -- 2.43.0