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[85.229.7.191]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c292c14c6a8sm90988566b.47.2026.09.09.01.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 01:51:19 -0700 (PDT) From: Anders Roxell To: u-boot@lists.u-boot-project.org Cc: marek.vasut@mailbox.org, trini@konsulko.com, ilias.apalodimas@linaro.org, michal.simek@amd.com, lukma@denx.de, alchark@flipper.net, jerome.forissier@arm.com, dlechner@baylibre.com, anshuld@ti.com, sjg@chromium.org, Thinh.Nguyen@synopsys.com, Anders Roxell Subject: [PATCH v8 09/25] usb: dwc3: ep0: flush and invalidate cache around ep0 transfers Date: Wed, 9 Sep 2026 10:49:59 +0200 Message-ID: <20260909085015.2480097-10-anders.roxell@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260909085015.2480097-1-anders.roxell@linaro.org> References: <20260909085015.2480097-1-anders.roxell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Wed, 09 Sep 2026 12:45:47 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org The dwc3 driver was synced from Linux v6.16. In Linux the DMA api keeps the trb and the buffers in sync with the controller. In u-boot the ep0 trb and buffers come from dma_alloc_coherent, which is just cached memory, not coherent. Nothing syncs them around the controller dma, so we must flush and invalidate by hand. U-boot did this before, the resync dropped it. Without cache maintenance the controller reads a stale trb and a stale buffer, and reads back stale status. The device answers GET_DESCRIPTOR with garbage, so the host fails to enumerate with -71 (EPROTO). Flush the trb and the buffer before the controller reads them. Invalidate the setup packet, the status write back and the OUT data buffer after the controller writes them. Tested on BeagleBoard-X15 with DFU. Reported-by: Anshul Dalal Signed-off-by: Anders Roxell --- drivers/usb/dwc3/ep0.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index e81404e11405..f82c0f7e6dec 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -55,6 +55,9 @@ static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep, else trb->ctrl |= (DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_LST); + + dwc3_flush_cache((uintptr_t)buf_dma, len); + dwc3_flush_cache((uintptr_t)trb, sizeof(*trb)); } static int dwc3_ep0_start_trans(struct dwc3_ep *dep) @@ -812,6 +815,8 @@ static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, int ret = -EINVAL; u32 len; + dwc3_invalidate_cache((uintptr_t)ctrl, sizeof(*ctrl)); + if (!dwc->gadget_driver || !dwc->softconnect || !dwc->connected) goto out; @@ -857,6 +862,8 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc, dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; trb = dwc->ep0_trb; + dwc3_invalidate_cache((uintptr_t)trb, sizeof(*trb) * 2); + r = next_request(&ep0->pending_list); if (!r) return; @@ -874,6 +881,9 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc, length = trb->size & DWC3_TRB_SIZE_MASK; transferred = ur->length - length; + + if (ur->buf && !r->direction) + dwc3_invalidate_cache((uintptr_t)ur->dma, ur->length); ur->actual += transferred; if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && -- 2.53.0