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[85.229.7.191]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c262f97f1a3sm557381266b.19.2026.09.09.01.53.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 01:53:26 -0700 (PDT) From: Anders Roxell To: u-boot@lists.u-boot-project.org Cc: marek.vasut@mailbox.org, trini@konsulko.com, ilias.apalodimas@linaro.org, michal.simek@amd.com, lukma@denx.de, alchark@flipper.net, jerome.forissier@arm.com, dlechner@baylibre.com, anshuld@ti.com, sjg@chromium.org, Thinh.Nguyen@synopsys.com, Anders Roxell , Jerome Forissier , Jens Wiklander Subject: [PATCH v8 24/25] usb: host: xhci: fix up after the resync Date: Wed, 9 Sep 2026 10:50:14 +0200 Message-ID: <20260909085015.2480097-25-anders.roxell@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260909085015.2480097-1-anders.roxell@linaro.org> References: <20260909085015.2480097-1-anders.roxell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Wed, 09 Sep 2026 12:45:47 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Adapt the xhci glue to the re-imported xhci-ext-caps.h. Co-developed-by: Jerome Forissier Signed-off-by: Jerome Forissier Co-developed-by: Jens Wiklander Signed-off-by: Jens Wiklander Signed-off-by: Anders Roxell --- drivers/usb/host/xhci-dwc3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 3504a7cf42ce..488d39fe72fd 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -51,7 +51,7 @@ static void dwc3_phy_reset(struct dwc3 *dwc3_reg) clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); } -void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) +static void _dwc3_core_soft_reset(struct dwc3 *dwc3_reg) { /* Before Resetting PHY, put Core in Reset */ setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); @@ -79,7 +79,7 @@ int dwc3_core_init(struct dwc3 *dwc3_reg) return -1; } - dwc3_core_soft_reset(dwc3_reg); + _dwc3_core_soft_reset(dwc3_reg); dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); -- 2.53.0