From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A37953A8A1; Wed, 9 Sep 2026 13:56:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788962174; cv=none; b=BYmUZWpu/24VQ5ZbIjPz6UkI2ucoIJBjCq5MX0Goi+or52KCQ7/rWnEDR8sEiAsahCsmQjLUJIE+bPbcj0kJLyvIeS6ZPzf3kMyMbOQdymrRF/Is8bAj/Pl1v+uRzmz35bATO/OYBdNFwpZ8BNzEGhFaLxmhFeqfMFjTa41ztqk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788962174; c=relaxed/simple; bh=RecrP4FJDTRspJ3qr5QeUPajHPDAtcj+ldt9PMNXWUE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GnsN09f/CZZLCSSMC3SWO5YFDhL1SCpCbpgntvqVEMWgEnKQinTlk1cfpx8eV1OYR/IA5NVTfZGC5gtTFWEvmGlbM6rcEfp2SRXSUkXRsZpVIvkPX1/0iG4s42J+jDPEtQKQJkoWpIS3dxJT+hTbrsWWSdEcDAiUlgWiqUrTgck= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=dLHmQW6e; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="dLHmQW6e" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7CCFE1F00A3A; Wed, 9 Sep 2026 13:56:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1788962172; bh=hzv1hc/GTj1Xt07a2ucWO1WsenmWPDR5AhV4rKk4BGM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=dLHmQW6e89lh36gsYMN56n1pMebJWHPpKT5hd1Plbe0gPuc+LqWfYJQeJ0z6xOIZ+ 0zXA+6aIoKOK7kF5sSZPMQgpOqtHkW+dTcQu9cKhWeLImvCMRK+A3GUBoionisdzXx oe/lWhENzeUF1rlDKSbIWdK/rTvBvKplOm/TRmFQ= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, James Hilliard , Miquel Raynal Subject: [PATCH 7.2 198/556] mtd: rawnand: sunxi: fix H6/H616 controller timings Date: Wed, 9 Sep 2026 15:37:58 +0200 Message-ID: <20260909134237.365718583@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260909134230.441546314@linuxfoundation.org> References: <20260909134230.441546314@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 7.2-stable review patch. If anyone has any objections, please let me know. ------------------ From: James Hilliard commit 15a3cbce32994141252bb4ecfe3ff3a5d22d0b4f upstream. The NAND timing calculation assumes that command and address setup and hold intervals T1-T4, T7 and T11 each take one controller clock. It also uses the original A10 delay encodings for tWB, tADL, tWHR and tRHW. The H6/H616 NDFC defines the setup and hold intervals as two internal clock cycles and uses different delay encodings. Add the H616 timing characteristics and select them through the controller capability data so the clock solver and timing fields match the hardware. Fixes: 88fd4e4deae8 ("mtd: rawnand: sunxi: Add support for H616 nand controller") Cc: stable@vger.kernel.org Signed-off-by: James Hilliard Signed-off-by: Miquel Raynal Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/nand/raw/sunxi_nand.c | 49 +++++++++++++++++++++++++++----------- 1 file changed, 36 insertions(+), 13 deletions(-) --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -241,6 +241,8 @@ struct sunxi_nand_hw_ecc { /* Delay arrays contain internal NDFC clock cycles for field values 0 to 3. */ struct sunxi_nfc_timings { + /* Internal clock cycles used by T1-T4, T7 and T11. */ + u8 setup_cycles; s32 tWB[SUNXI_NFC_TIMING_STEPS]; s32 tADL[SUNXI_NFC_TIMING_STEPS]; s32 tWHR[SUNXI_NFC_TIMING_STEPS]; @@ -1680,12 +1682,21 @@ static int sunxi_nfc_hw_ecc_write_oob(st } static const struct sunxi_nfc_timings sun4i_a10_nfc_timings = { + .setup_cycles = 1, .tWB = { 6, 12, 16, 20 }, .tADL = { 7, 15, 23, 31 }, .tWHR = { 7, 15, 23, 31 }, .tRHW = { 4, 8, 12, 20 }, }; +static const struct sunxi_nfc_timings sun50i_h616_nfc_timings = { + .setup_cycles = 2, + .tWB = { 28, 44, 60, 76 }, + .tADL = { 0, 12, 28, 44 }, + .tWHR = { 0, 12, 28, 44 }, + .tRHW = { 8, 24, 40, 56 }, +}; + static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration, u32 clk_period) { @@ -1720,20 +1731,28 @@ static int sunxi_nfc_setup_interface(str return -ENOTSUPP; /* T1 <=> tCLS */ - if (timings->tCLS_min > min_clk_period) - min_clk_period = timings->tCLS_min; + if (timings->tCLS_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period = DIV_ROUND_UP(timings->tCLS_min, + nfc_timings->setup_cycles); /* T2 <=> tCLH */ - if (timings->tCLH_min > min_clk_period) - min_clk_period = timings->tCLH_min; + if (timings->tCLH_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period = DIV_ROUND_UP(timings->tCLH_min, + nfc_timings->setup_cycles); /* T3 <=> tCS */ - if (timings->tCS_min > min_clk_period) - min_clk_period = timings->tCS_min; + if (timings->tCS_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period = DIV_ROUND_UP(timings->tCS_min, + nfc_timings->setup_cycles); /* T4 <=> tCH */ - if (timings->tCH_min > min_clk_period) - min_clk_period = timings->tCH_min; + if (timings->tCH_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period = DIV_ROUND_UP(timings->tCH_min, + nfc_timings->setup_cycles); /* T5 <=> tWP */ if (timings->tWP_min > min_clk_period) @@ -1744,8 +1763,10 @@ static int sunxi_nfc_setup_interface(str min_clk_period = timings->tWH_min; /* T7 <=> tALS */ - if (timings->tALS_min > min_clk_period) - min_clk_period = timings->tALS_min; + if (timings->tALS_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period = DIV_ROUND_UP(timings->tALS_min, + nfc_timings->setup_cycles); /* T8 <=> tDS */ if (timings->tDS_min > min_clk_period) @@ -1760,8 +1781,10 @@ static int sunxi_nfc_setup_interface(str min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3); /* T11 <=> tALH */ - if (timings->tALH_min > min_clk_period) - min_clk_period = timings->tALH_min; + if (timings->tALH_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period = DIV_ROUND_UP(timings->tALH_min, + nfc_timings->setup_cycles); /* T12 <=> tRP */ if (timings->tRP_min > min_clk_period) @@ -2670,7 +2693,7 @@ static const struct sunxi_nfc_caps sunxi .nuser_data_tab = ARRAY_SIZE(sunxi_user_data_len_h6), .max_ecc_steps = 32, .sram_size = 8192, - .timings = &sun4i_a10_nfc_timings, + .timings = &sun50i_h616_nfc_timings, }; static const struct of_device_id sunxi_nfc_ids[] = {