From: sashiko-bot@kernel.org
To: "Wei-Lin Chang" <weilin.chang@arm.com>
Cc: "Marc Zyngier" <maz@kernel.org>,
kvmarm@lists.linux.dev, "Oliver Upton" <oupton@kernel.org>
Subject: Re: [PATCH v1 1/3] KVM: arm64: nv: Don't advertise FEAT_LPA2 for guest stage-1
Date: Wed, 09 Sep 2026 22:44:58 +0000 [thread overview]
Message-ID: <20260909224458.E7F0D1F00898@smtp.kernel.org> (raw)
In-Reply-To: <20260909222015.3046432-2-weilin.chang@arm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Equality checks for TGRAN4 and TGRAN16 fail to mask future architectural enum values, leaking unsupported hardware capabilities to NV guests.
--
commit 6c2ebbb5542b3e22eaee90b7cf8d8cbbc9704e7c
Author: Wei-Lin Chang <weilin.chang@arm.com>
KVM: arm64: nv: Don't advertise FEAT_LPA2 for guest stage-1
There is no FEAT_LPA2 support for NV guests as of now, but we missed
limiting it for the non-stage-2 granule size fields (TGRAN4, TGRAN16) in
ID_AA64MMFR0_EL1. Add the sanitisation.
> diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
> index 17123f0b6daba..4d1884b32fc48 100644
> --- a/arch/arm64/kvm/nested.c
> +++ b/arch/arm64/kvm/nested.c
> @@ -1731,6 +1731,19 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val)
> /* Hide CNTPOFF if present */
> val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64MMFR0_EL1, ECV, IMP);
>
> + /* NV does not support FEAT_LPA2. */
> + if (SYS_FIELD_GET(ID_AA64MMFR0_EL1, TGRAN4, val) ==
> + ID_AA64MMFR0_EL1_TGRAN4_52_BIT) {
[Severity: Medium]
Will this exact equality check fail to mask future architectural enum values?
If future hardware implements a capability enum value greater than 52_BIT for
TGRAN4, this check will evaluate to false, leaking the unsupported capability
to NV guests.
Could this be capped instead, perhaps using inequalities or the
ID_REG_LIMIT_FIELD_ENUM macro, to maintain forward compatibility?
> + val &= ~ID_AA64MMFR0_EL1_TGRAN4;
> + val |= SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, TGRAN4, IMP);
> + }
> +
> + if (SYS_FIELD_GET(ID_AA64MMFR0_EL1, TGRAN16, val) ==
> + ID_AA64MMFR0_EL1_TGRAN16_52_BIT) {
[Severity: Medium]
Similarly, will this exact equality check fail to mask future unsigned capability
values greater than 52_BIT for TGRAN16?
> + val &= ~ID_AA64MMFR0_EL1_TGRAN16;
> + val |= SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, TGRAN16, IMP);
> + }
> +
> /* Disallow unsupported S2 page sizes */
> switch (PAGE_SIZE) {
> case SZ_64K:
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260909222015.3046432-1-weilin.chang@arm.com?part=1
next prev parent reply other threads:[~2026-09-09 22:45 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-09 22:20 [PATCH v1 0/3] KVM: arm64: Properly advertise !FEAT_LPA2 for NV Wei-Lin Chang
2026-09-09 22:20 ` [PATCH v1 1/3] KVM: arm64: nv: Don't advertise FEAT_LPA2 for guest stage-1 Wei-Lin Chang
2026-09-09 22:44 ` sashiko-bot [this message]
2026-09-10 10:56 ` Wei-Lin Chang
2026-09-11 8:22 ` Marc Zyngier
2026-09-11 9:08 ` Marc Zyngier
2026-09-09 22:20 ` [PATCH v1 2/3] arm64: sysreg: Add TCR_EL2 to sysreg infrastructure Wei-Lin Chang
2026-09-09 22:38 ` sashiko-bot
2026-09-10 10:58 ` Wei-Lin Chang
2026-09-11 8:45 ` Marc Zyngier
2026-09-10 11:54 ` Mark Brown
2026-09-09 22:20 ` [PATCH v1 3/3] KVM: arm64: Convert TCR_EL2 to config-driven sanitisation Wei-Lin Chang
2026-09-11 9:04 ` Marc Zyngier
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