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Thu, 10 Sep 2026 02:54:02 -0700 (PDT) Received: from thefoxflat ([2404:c0:7029:b3c6:7b99:50ff:b405:5c31]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39d7e77498csm3849455a91.3.2026.09.10.02.53.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2026 02:54:02 -0700 (PDT) From: Reza Kurniawan To: u-boot@lists.u-boot-project.org Cc: Reza Kurniawan , Casey Connolly , Lukasz Majewski , Neil Armstrong , Sumit Garg , Tom Rini , u-boot-qcom@groups.io Subject: [PATCH 3/4] clk: qcom: Add an option to poll for GDSCR GDSC_POWER_ON bit Date: Thu, 10 Sep 2026 09:41:46 +0000 Message-ID: <20260910095339.110427-4-imkyufie@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910095339.110427-1-imkyufie@gmail.com> References: <20260910095339.110427-1-imkyufie@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Thu, 10 Sep 2026 12:14:04 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Some SoCs such as MSM8917 poll its GDSC power domains by reading GDSCR directly, as opposed to GDSCR + CFG_GDSCR_OFFSET. Add a poll_gdscr flag to struct qcom_power_map to facilitate those SoCs. Signed-off-by: Reza Kurniawan --- drivers/clk/qcom/clock-qcom.c | 24 +++++++++++++----------- drivers/clk/qcom/clock-qcom.h | 1 + 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 6b46d9db7..754ff4ff4 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -505,9 +505,9 @@ U_BOOT_DRIVER(qcom_reset) = { static int qcom_power_set(struct power_domain *pwr, bool on) { struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(pwr->dev); - void __iomem *base = dev_get_priv(pwr->dev); + void __iomem *base = dev_get_priv(pwr->dev), *poll_addr; const struct qcom_power_map *map; - u32 value; + u32 value, mask; int ret; if (pwr->id >= data->num_power_domains) @@ -527,19 +527,21 @@ static int qcom_power_set(struct power_domain *pwr, bool on) writel(value, base + map->reg); - if (on) - ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET, + poll_addr = base + map->reg; + if (map->poll_gdscr) { + /* Some SOCs such as MSM8917 poll at GDSCR */ + ret = readl_poll_timeout(poll_addr, value, - (value & GDSC_POWER_UP_COMPLETE) || - (value & GDSC_PWR_ON_MASK), + (!!(value & GDSC_PWR_ON_MASK) == on), GDSC_STATUS_POLL_TIMEOUT_US); - - else - ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET, + } else { + mask = on ? GDSC_POWER_UP_COMPLETE : GDSC_POWER_DOWN_COMPLETE; + ret = readl_poll_timeout(poll_addr + CFG_GDSCR_OFFSET, value, - (value & GDSC_POWER_DOWN_COMPLETE) || - !(value & GDSC_PWR_ON_MASK), + (value & mask) || + !!(value & GDSC_PWR_ON_MASK) == on, GDSC_STATUS_POLL_TIMEOUT_US); + } if (ret == -ETIMEDOUT) printf("WARNING: GDSC %lu is stuck during power on/off\n", diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 3a4550d85..0b514cc1f 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -76,6 +76,7 @@ struct qcom_reset_map { struct qcom_power_map { unsigned int reg; + bool poll_gdscr; }; struct clk; -- 2.55.0