From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B5F558F073 for ; Thu, 10 Sep 2026 19:08:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789067336; cv=none; b=iJ5X8AQZ4+OR0JaQvz2xDRg43gHzwZVR5IrYshF5ILJCtcwm/J5+vEQYsXpF2XBNoPTupuyRcYQ0s2DgrS+pDFd5+UjaCPfrqCZEu//1odqNQQMF8IzwZkUQHowaVoSE0QF+3QkZO+3pxz/D0vdEv7bvLzN6pks2KPMeTRNRl40= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789067336; c=relaxed/simple; bh=HTObshrFRb/YjZVIlJEqwwaLajwr7whwMhyhLxRjTNU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W3L6xDzgksEervZqXHOq17HYkNoFDaUIGR2+dx7NGTnVCND/vUzY3+6txl/M1DcslxfdfUWLPG9sb2A972hUbDkTMYNNy364iF+WQd1Qtrul3/o/3YbNumU2CUKoBwTywESebNBBqIfcwefqs0WS0gdLobgmjSM9ouMEYgbGMNU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XosiQhXB; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XosiQhXB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C24901F00893; Thu, 10 Sep 2026 19:08:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1789067334; bh=SmCpFA/ShAwqTVWaWaJse/brTkUkFGHSX0wT4t/O5JI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=XosiQhXBJBiDHWVWN3PCKXtMIkGZRda8mZhiunX8xHf9DF0Fz7I8LHiUQSapj87fk z27pkHsLkQqH6EXGHPH9WTqleH4/65V9lDCaRMB1Dwijq/iek4mzNdfp/DR4iMzrXf LIsRFe883485jeGEPNk+QGyO/BPQ1r0tiP08qpt51FtumELLUGF+/qbrEhpAxOeWts yOnP1Jo83RWw/8FpS95LYKeGgS/N4SB6ZMqaesapnK597/g59hpsPdXmhaLFfwxEgQ dyXWzkIDrWpIgGAGzVN10qPWDtvSmV2YYxBPFwlr/3utlCJr3PpnG0l/cLavcXE1OR TWfhSn105iLLA== From: Sasha Levin To: stable@vger.kernel.org Cc: Yabin Cui , Ingo Molnar , James Clark , Anshuman Khandual , Peter Zijlstra , Arnaldo Carvalho de Melo , Jiri Olsa , Alexander Shishkin , Mark Rutland , Namhyung Kim , Sasha Levin Subject: [PATCH 6.12.y 1/2] perf/aux: Allocate non-contiguous AUX pages by default Date: Thu, 10 Sep 2026 15:08:51 -0400 Message-ID: <20260910190852.1454402-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <2026090959-treadmill-straddle-c245@gregkh> References: <2026090959-treadmill-straddle-c245@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Yabin Cui [ Upstream commit 18049c8cff9cc89daadc4df6975f7d9069638926 ] perf always allocates contiguous AUX pages based on aux_watermark. However, this contiguous allocation doesn't benefit all PMUs. For instance, ARM SPE and TRBE operate with virtual pages, and Coresight ETR allocates a separate buffer. For these PMUs, allocating contiguous AUX pages unnecessarily exacerbates memory fragmentation. This fragmentation can prevent their use on long-running devices. This patch modifies the perf driver to be memory-friendly by default, by allocating non-contiguous AUX pages. For PMUs requiring contiguous pages (Intel BTS and some Intel PT), the existing PERF_PMU_CAP_AUX_NO_SG capability can be used. For PMUs that don't require but can benefit from contiguous pages (some Intel PT), a new capability, PERF_PMU_CAP_AUX_PREFER_LARGE, is added to maintain their existing behavior. Signed-off-by: Yabin Cui Signed-off-by: Ingo Molnar Reviewed-by: James Clark Reviewed-by: Anshuman Khandual Cc: Peter Zijlstra Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Alexander Shishkin Cc: Mark Rutland Cc: Namhyung Kim Link: https://lore.kernel.org/r/20250508232642.148767-1-yabinc@google.com Stable-dep-of: 8767b4d73018 ("perf/x86/intel: Remove anythread_deprecated bit from perf_capabilities") Signed-off-by: Sasha Levin --- arch/x86/events/intel/pt.c | 2 ++ include/linux/perf_event.h | 1 + kernel/events/ring_buffer.c | 29 ++++++++++++++++++++--------- 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index a087bc0c54987..acdff93985504 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -1797,6 +1797,8 @@ static __init int pt_init(void) if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG; + else + pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_PREFER_LARGE; pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE; pt_pmu.pmu.attr_groups = pt_attr_groups; diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index c2bd4bc45a27b..be6ddf1961534 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -301,6 +301,7 @@ struct perf_event_pmu_context; #define PERF_PMU_CAP_AUX_OUTPUT 0x0080 #define PERF_PMU_CAP_EXTENDED_HW_TYPE 0x0100 #define PERF_PMU_CAP_AUX_PAUSE 0x0200 +#define PERF_PMU_CAP_AUX_PREFER_LARGE 0x0400 /** * pmu::scope diff --git a/kernel/events/ring_buffer.c b/kernel/events/ring_buffer.c index 6ecbbc57cdfde..b4edac7d9cd34 100644 --- a/kernel/events/ring_buffer.c +++ b/kernel/events/ring_buffer.c @@ -680,7 +680,15 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, { bool overwrite = !(flags & RING_BUFFER_WRITABLE); int node = (event->cpu == -1) ? -1 : cpu_to_node(event->cpu); - int ret = -ENOMEM, max_order; + bool use_contiguous_pages = event->pmu->capabilities & ( + PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_AUX_PREFER_LARGE); + /* + * Initialize max_order to 0 for page allocation. This allocates single + * pages to minimize memory fragmentation. This is overridden if the + * PMU needs or prefers contiguous pages (use_contiguous_pages = true). + */ + int max_order = 0; + int ret = -ENOMEM; if (!has_aux(event)) return -EOPNOTSUPP; @@ -690,8 +698,8 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, if (!overwrite) { /* - * Watermark defaults to half the buffer, and so does the - * max_order, to aid PMU drivers in double buffering. + * Watermark defaults to half the buffer, to aid PMU drivers + * in double buffering. */ if (!watermark) watermark = min_t(unsigned long, @@ -699,16 +707,19 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, (unsigned long)nr_pages << (PAGE_SHIFT - 1)); /* - * Use aux_watermark as the basis for chunking to - * help PMU drivers honor the watermark. + * If using contiguous pages, use aux_watermark as the basis + * for chunking to help PMU drivers honor the watermark. */ - max_order = get_order(watermark); + if (use_contiguous_pages) + max_order = get_order(watermark); } else { /* - * We need to start with the max_order that fits in nr_pages, - * not the other way around, hence ilog2() and not get_order. + * If using contiguous pages, we need to start with the + * max_order that fits in nr_pages, not the other way around, + * hence ilog2() and not get_order. */ - max_order = ilog2(nr_pages); + if (use_contiguous_pages) + max_order = ilog2(nr_pages); watermark = 0; } -- 2.53.0