From: sashiko-bot@kernel.org
To: "Vladimir Nedoshivin" <gvozd188@mail.ru>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH] PCI: vmd: Enable interrupt ordering quirk for Arrow Lake
Date: Thu, 10 Sep 2026 20:14:08 +0000 [thread overview]
Message-ID: <20260910201409.456AE1F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260910200539.10862-1-gvozd188@mail.ru>
> Intel Arrow Lake VMD device 0xad0b is affected by ARL004. The VMD may
> signal an MSI before preceding posted writes from the child device have
> reached memory, which can cause the demuxed handler to observe stale
> completion data.
>
> The existing VMD_FEAT_INTERRUPT_QUIRK implements Intel's documented
> workaround by issuing a configuration-space read to the MSI initiator
> before dispatching the interrupt.
>
> Enable the existing quirk for 0xad0b as well as 0x7d0b and make the
> comments describe both MTL016 and ARL004.
>
> Tested on an MSI Vector 17 HX AI with Intel VMD 8086:ad0b and an NVMe
> device behind VMD. With the quirk enabled, the NVMe completion stalls
> observed without the workaround are no longer reproduced.
>
> Link: https://bugs.launchpad.net/bugs/2166325
> Signed-off-by: Vladimir Nedoshivin <gvozd188@mail.ru>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260910200539.10862-1-gvozd188@mail.ru?part=1
next prev parent reply other threads:[~2026-09-10 20:14 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-10 20:05 [PATCH] PCI: vmd: Enable interrupt ordering quirk for Arrow Lake Vladimir Nedoshivin
2026-09-10 20:14 ` sashiko-bot [this message]
2026-10-01 23:07 ` Bjorn Helgaas
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