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Fri, 11 Sep 2026 12:28:00 +0000 (UTC) Received: from localhost (headnet05.pony-001.prod.iad2.dc.redhat.com [10.2.32.117]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id B7BD91800581; Fri, 11 Sep 2026 12:27:59 +0000 (UTC) From: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Date: Fri, 11 Sep 2026 16:27:30 +0400 Subject: [PATCH 07/10] target/sparc64: expose system registers via GDB MIME-Version: 1.0 Message-Id: <20260911-query-reg-v1-7-0c04f0c02cf3@redhat.com> References: <20260911-query-reg-v1-0-0c04f0c02cf3@redhat.com> In-Reply-To: <20260911-query-reg-v1-0-0c04f0c02cf3@redhat.com> To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Zhao Liu , Peter Maydell , Chinmay Rath , Nicholas Piggin , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Paolo Bonzini , Laurent Vivier , Mark Cave-Ayland , Artyom Tarasenko , Helge Deller , Pierrick Bouvier , Warner Losh , Kyle Evans , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= X-Developer-Signature: v=1; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 X-Mimecast-MFC-PROC-ID: i6v-bQRAmVwHbv8CeBm3gZOYTP8kraAiKbFGUWRGvZ4_1789129681 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Add a sparc64-system.xml GDB feature that exposes asi, pstate, cansave, canrestore, otherwin, wstate, and cleanwin as read-only system registers through the GDB coprocessor interface. Signed-off-by: Marc-André Lureau --- configs/targets/sparc64-softmmu.mak | 2 +- gdbstub/gdb-xml/sparc64-system.xml | 22 +++++++++++++++++++++ target/sparc/gdbstub.c | 38 +++++++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+), 1 deletion(-) diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak index 4e621fb8e39e..7f2789136653 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,7 +1,7 @@ TARGET_ARCH=sparc64 TARGET_BASE_ARCH=sparc TARGET_BIG_ENDIAN=y -TARGET_XML_FILES=sparc64-cpu.xml sparc64-fpu.xml sparc64-cp0.xml +TARGET_XML_FILES=sparc64-cpu.xml sparc64-fpu.xml sparc64-cp0.xml sparc64-system.xml TARGET_LONG_BITS=64 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y diff --git a/gdbstub/gdb-xml/sparc64-system.xml b/gdbstub/gdb-xml/sparc64-system.xml new file mode 100644 index 000000000000..e00baedb467e --- /dev/null +++ b/gdbstub/gdb-xml/sparc64-system.xml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index 2874ce1b3501..ca23a4a94532 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -266,6 +266,39 @@ static int sparc_cp0_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) #endif } +#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) +static int sparc64_gdb_read_system_register(CPUState *cs, GByteArray *buf, + int n) +{ + CPUSPARCState *env = cpu_env(cs); + + switch (n) { + case 0: + return gdb_get_reg32(buf, env->asi); + case 1: + return gdb_get_reg32(buf, env->pstate); + case 2: + return gdb_get_reg32(buf, env->cansave); + case 3: + return gdb_get_reg32(buf, env->canrestore); + case 4: + return gdb_get_reg32(buf, env->otherwin); + case 5: + return gdb_get_reg32(buf, env->wstate); + case 6: + return gdb_get_reg32(buf, env->cleanwin); + default: + return 0; + } +} + +static int sparc64_gdb_write_system_register(CPUState *cs, uint8_t *buf, int n) +{ + /* These registers are exposed for inspection only. Ignore writes. */ + return 4; +} +#endif + void sparc_cpu_register_gdb_regs(CPUState *cs) { #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) @@ -282,5 +315,10 @@ void sparc_cpu_register_gdb_regs(CPUState *cs) gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register, sparc_cp0_gdb_write_register, gdb_find_static_feature("sparc64-cp0.xml")); +#ifndef CONFIG_USER_ONLY + gdb_register_coprocessor(cs, sparc64_gdb_read_system_register, + sparc64_gdb_write_system_register, + gdb_find_static_feature("sparc64-system.xml")); +#endif #endif } -- 2.55.0.543.g5ebe2ebe4ea8