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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.6 on 10.30.177.95 Received-SPF: pass client-ip=170.10.133.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The core GDB XML uses ABI names (zero, ra, sp, fp, ft0, fs0, etc.) but users also refer to registers by their numeric names (x0-x31, f0-f31) and the s0 alias for fp. The legacy MonitorDef mechanism supported both via split "x0/zero" name matching. Register a feature that maps: - x0-x31 and s0 to the corresponding core integer registers - x0h-x31h and their ABI aliases (zeroh, rah, ...) to env->gprh[] - f0-f31 to the corresponding FPU registers (when FPU is present) This preserves full HMP $register compatibility after the MonitorDef removal. Signed-off-by: Marc-André Lureau --- configs/targets/riscv32-linux-user.mak | 2 +- configs/targets/riscv32-softmmu.mak | 2 +- configs/targets/riscv64-bsd-user.mak | 2 +- configs/targets/riscv64-linux-user.mak | 2 +- configs/targets/riscv64-softmmu.mak | 2 +- gdbstub/gdb-xml/riscv-32bit-alias.xml | 105 ++++++++++++++++++++++++++++++ gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml | 40 ++++++++++++ gdbstub/gdb-xml/riscv-64bit-alias.xml | 105 ++++++++++++++++++++++++++++++ gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml | 46 +++++++++++++ target/riscv/gdbstub.c | 43 ++++++++++++ 10 files changed, 344 insertions(+), 5 deletions(-) diff --git a/configs/targets/riscv32-linux-user.mak b/configs/targets/riscv32-linux-user.mak index d88fdf5e1b2f..8ee14fa14383 100644 --- a/configs/targets/riscv32-linux-user.mak +++ b/configs/targets/riscv32-linux-user.mak @@ -1,7 +1,7 @@ TARGET_ARCH=riscv32 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv -TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml +TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y TARGET_SYSTBL_ABI=32 diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak index 5d5016d00832..c717940344f0 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -1,6 +1,6 @@ TARGET_ARCH=riscv32 TARGET_BASE_ARCH=riscv -TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml +TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml # needed by boot.c TARGET_NEED_FDT=y TARGET_LONG_BITS=32 diff --git a/configs/targets/riscv64-bsd-user.mak b/configs/targets/riscv64-bsd-user.mak index 5b4e138099fc..1d37e018c871 100644 --- a/configs/targets/riscv64-bsd-user.mak +++ b/configs/targets/riscv64-bsd-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv -TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml +TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml TARGET_LONG_BITS=64 TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y diff --git a/configs/targets/riscv64-linux-user.mak b/configs/targets/riscv64-linux-user.mak index 35621520c560..564d15aaca8c 100644 --- a/configs/targets/riscv64-linux-user.mak +++ b/configs/targets/riscv64-linux-user.mak @@ -1,7 +1,7 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv -TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml +TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y TARGET_SYSTBL_ABI=64 diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak index a10dc03c04c8..28bfcdc575fb 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -1,7 +1,7 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_KVM_HAVE_GUEST_DEBUG=y -TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-32bit-cpu.xml riscv-32bit-virtual.xml +TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-32bit-cpu.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml # needed by boot.c TARGET_NEED_FDT=y TARGET_LONG_BITS=64 diff --git a/gdbstub/gdb-xml/riscv-32bit-alias.xml b/gdbstub/gdb-xml/riscv-32bit-alias.xml new file mode 100644 index 000000000000..a00a86ebdf95 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-32bit-alias.xml @@ -0,0 +1,105 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml b/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml new file mode 100644 index 000000000000..3935f72ea289 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/riscv-64bit-alias.xml b/gdbstub/gdb-xml/riscv-64bit-alias.xml new file mode 100644 index 000000000000..28781b230226 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-64bit-alias.xml @@ -0,0 +1,105 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml b/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml new file mode 100644 index 000000000000..13e6b341a0f8 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index f279f4ab2461..6694fa86fd84 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -336,16 +336,59 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg) return &cpu->dyn_vreg_feature; } +/* x0-x31, s0, then pairs of numeric and ABI high-half aliases. */ +static int riscv_gdb_get_alias(CPUState *cs, GByteArray *buf, int n) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + uint64_t val; + + if (n < 33) { + return riscv_cpu_gdb_read_register(cs, buf, n == 32 ? 8 : n); + } + + val = cpu->env.gprh[(n - 33) / 2]; + if (riscv_cpu_is_32bit(cpu)) { + return gdb_get_reg32(buf, val); + } + return gdb_get_reg64(buf, val); +} + +static int riscv_gdb_set_alias(CPUState *cs, uint8_t *buf, int n) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8; + + if (n < 33) { + return riscv_cpu_gdb_write_register(cs, buf, n == 32 ? 8 : n); + } + + env->gprh[(n - 33) / 2] = ldn(env, buf, regsz); + return regsz; +} + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; + + gdb_register_coprocessor(cs, riscv_gdb_get_alias, riscv_gdb_set_alias, + gdb_find_static_feature(riscv_cpu_is_32bit(cpu) ? + "riscv-32bit-alias.xml" : + "riscv-64bit-alias.xml")); + if (env->misa_ext & RVD) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, gdb_find_static_feature("riscv-64bit-fpu.xml")); + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, + riscv_gdb_set_fpu, + gdb_find_static_feature("riscv-64bit-fpu-alias.xml")); } else if (env->misa_ext & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, gdb_find_static_feature("riscv-32bit-fpu.xml")); + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, + riscv_gdb_set_fpu, + gdb_find_static_feature("riscv-32bit-fpu-alias.xml")); } if (cpu->cfg.ext_zve32x) { GDBFeature *feature = -- 2.55.0.543.g5ebe2ebe4ea8