From: sashiko-bot@kernel.org
To: "Suraj Kandpal" <suraj.kandpal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 03/10] drm/i915/dp_mst: Limit M/N ratio for MST
Date: Fri, 11 Sep 2026 04:30:19 +0000 [thread overview]
Message-ID: <20260911043019.902A11F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260911041449.3699400-4-suraj.kandpal@intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The M/N ratio check in mst_connector_mode_valid_ctx uses the link rate of the max bandwidth configuration, falsely rejecting valid display modes that could be supported by a narrower but faster configuration.
--
commit 98416996dd21ed919f77966254ec5cd4baea6754
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
drm/i915/dp_mst: Limit M/N ratio for MST
This commit adds M/N ratio limits for DisplayPort MST configurations by
pruning modes in mst_connector_mode_valid_ctx() that exceed hardware
limits. It mirrors the SST mode validation logic.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 6a869d0f6ffc0..796374cebf051 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
[ ... ]
> @@ -1564,6 +1564,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
> min_link_bpp_x16,
> bw_overhead_flags);
>
> + if (!intel_dp_can_support_m_n(display, mode->clock, max_link_clock)) {
> + *status = MODE_CLOCK_HIGH;
> + return 0;
> + }
> +
[Severity: Medium]
The commit message states this check is added "using the highest link rate
available", mirroring the SST mode_valid check. However, max_link_clock
here is derived from max_bw_config.
Could this falsely reject valid display modes if the link capabilities
result in a max bandwidth configuration with a lower symbol clock than an
alternative configuration?
For example, if max_bw_config falls back to RBR x 4 (162MHz) but an
alternative HBR x 2 (270MHz) configuration is available, a mode's pixel
clock might exceed the M/N limit for the 162MHz config but safely fit
within the bandwidth and M/N limits of the 270MHz configuration. Does this
logic prematurely restrict those modes to the M/N ratio of the max
bandwidth config?
> /*
> * TODO:
> * - Also check if compression would allow for the mode
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260911041449.3699400-1-suraj.kandpal@intel.com?part=3
next prev parent reply other threads:[~2026-09-11 4:30 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-11 4:14 [PATCH 00/10] Implement Wa_14021768792 to bypass m_n ratio limit Suraj Kandpal
2026-09-11 4:14 ` [PATCH 01/10] drm/i915/display: Add helper to compute link M/N ratio for reuse Suraj Kandpal
2026-09-11 11:24 ` Jani Nikula
2026-09-11 11:28 ` Jani Nikula
2026-09-11 4:14 ` [PATCH 02/10] drm/i915/dp: Limit M/N ratio for DP SST Suraj Kandpal
2026-09-11 4:14 ` [PATCH 03/10] drm/i915/dp_mst: Limit M/N ratio for MST Suraj Kandpal
2026-09-11 4:30 ` sashiko-bot [this message]
2026-09-11 4:14 ` [PATCH 04/10] drm/i915/dp: Add M/N ratio check with warning for DP link config Suraj Kandpal
2026-09-11 4:14 ` [PATCH 05/10] drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14 Suraj Kandpal
2026-09-11 4:14 ` [PATCH 06/10] drm/i915/display_wa: Add support for Wa_14021768792 Suraj Kandpal
2026-09-11 4:14 ` [PATCH 07/10] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10 Suraj Kandpal
2026-09-11 4:29 ` sashiko-bot
2026-09-11 4:14 ` [PATCH 08/10] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n " Suraj Kandpal
2026-09-11 4:30 ` sashiko-bot
2026-09-11 4:14 ` [PATCH 09/10] drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass Suraj Kandpal
2026-09-11 4:14 ` [PATCH 10/10] drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35 Suraj Kandpal
2026-09-11 4:23 ` ✓ CI.KUnit: success for Implement Wa_14021768792 to bypass m_n ratio limit (rev6) Patchwork
2026-09-11 5:01 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-11 5:14 ` ✓ i915.CI.BAT: " Patchwork
2026-09-11 12:52 ` ✓ Xe.CI.FULL: " Patchwork
2026-09-11 23:52 ` ✗ i915.CI.Full: failure " Patchwork
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