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=?UTF-8?q?Enrique=20Hern=C3=A1ndez=20Bello?= Subject: [PATCH] PCI: rockchip: Skip the Tpvperl wait when power is already valid Date: Fri, 11 Sep 2026 11:49:52 +0100 Message-ID: <20260911104952.4190994-1-ehbello@gmail.com> X-Mailer: git-send-email 2.55.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260911_035013_710975_79922353 X-CRM114-Status: GOOD ( 18.94 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org U2luY2UgY29tbWl0IGM0N2Y5MGJlNGM4OSAoIlBDSTogcm9ja2NoaXAtaG9zdDogRml4CnJvY2tj aGlwX3BjaWVfaG9zdF9pbml0X3BvcnQoKSBQRVJTVCMgaGFuZGxpbmciKSwgYSBKTWljcm9uIEpN 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cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 03:50:10 -0700 (PDT) From: =?UTF-8?q?Enrique=20Hern=C3=A1ndez=20Bello?= To: shawn.lin@rock-chips.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com Cc: robh@kernel.org, heiko@sntech.de, dlemoal@kernel.org, linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, =?UTF-8?q?Enrique=20Hern=C3=A1ndez=20Bello?= Subject: [PATCH] PCI: rockchip: Skip the Tpvperl wait when power is already valid Date: Fri, 11 Sep 2026 11:49:52 +0100 Message-ID: <20260911104952.4190994-1-ehbello@gmail.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit c47f90be4c89 ("PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handling"), a JMicron JMB585 behind an rk3399 root port almost never becomes usable: the link trains normally, but the endpoint's configuration space never answers, so the device is not enumerated. On this controller a configuration read that gets no usable completion is reported as an external abort rather than as an all-ones response, which on arm64 brings the machine down. The change added an unconditional 100 ms sleep so that PERST# stays asserted for at least Tpvperl after power becomes valid. The wait is performed while PERST# is asserted, so it also extends the reset by 100 ms, and this endpoint does not tolerate the longer assertion. Tpvperl is counted from the supplies becoming valid (PCIe CEM r5.1, sec 2.9.2). On boards whose PCIe supplies are always-on -- vcc3v3_pcie on ROCK Pi 4 is regulator-always-on and regulator-boot-on -- power has been valid since boot, seconds before the driver probes, so the requirement is already met and the sleep only lengthens the reset. Record whether the supplies were already enabled before the driver enabled them, and skip the wait in that case. A supply that is already on at probe was brought up either by the bootloader or by the regulator core at boot, both of which precede a PCIe probe by far more than Tpvperl. When the driver really does bring the rails up, or on resume where vpcie0v9 has just been re-enabled, the full wait still happens, as it does if regulator_is_enabled() cannot tell. Measured on a ROCK Pi 4C with a Radxa Penta SATA HAT (JMB585) by booting repeatedly and counting how often the endpoint enumerated: unmodified .................................... 0 out of 84 boots with this patch ............................... 3 out of 3 boots other ways of dropping the same wait .......... 16 out of 16 boots Fisher's exact test, pooling the last two rows against the first, gives p = 4.1e-21. With the patch the endpoint enumerated on every boot and all four disks behind it came up. Each of the three PERST#-related changes that landed together in v6.11-rc1 was also reverted individually; only removing this wait made any difference. Moving the wait to before link training is enabled, rather than removing it, did not help (0 out of 15 boots), which is what identified the length of the PERST# assertion rather than any interaction with link training as the cause. The measurements were taken on 6.18, but the code in question is unchanged between v6.11 and v7.2. Fixes: c47f90be4c89 ("PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handling") Cc: stable@vger.kernel.org Signed-off-by: Enrique Hernández Bello --- --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -318,6 +318,7 @@ struct regulator *vpcie1v8; /* 1.8V power supply */ struct regulator *vpcie0v9; /* 0.9V power supply */ struct gpio_desc *perst_gpio; + bool supplies_pre_enabled; u32 lanes; u8 lanes_map; int link_gen; --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -314,7 +314,9 @@ rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, PCIE_CLIENT_CONFIG); - msleep(PCIE_T_PVPERL_MS); + if (!rockchip->supplies_pre_enabled) + msleep(PCIE_T_PVPERL_MS); + gpiod_set_value_cansleep(rockchip->perst_gpio, 1); msleep(PCIE_RESET_CONFIG_WAIT_MS); @@ -614,6 +616,23 @@ struct device *dev = rockchip->dev; int err; + /* + * Tpvperl is counted from the supplies becoming valid, and the wait + * for it happens with PERST# asserted, so it also lengthens the reset. + * A supply that is already enabled before this driver enables it was + * brought up either by the bootloader or by the regulator core at boot, + * both of which precede this probe by far more than Tpvperl, so the + * requirement is already met and the wait can be skipped. Treat an + * error from regulator_is_enabled() as "not known to be on" and wait. + */ + rockchip->supplies_pre_enabled = + (IS_ERR(rockchip->vpcie12v) || + regulator_is_enabled(rockchip->vpcie12v) > 0) && + (IS_ERR(rockchip->vpcie3v3) || + regulator_is_enabled(rockchip->vpcie3v3) > 0) && + regulator_is_enabled(rockchip->vpcie1v8) > 0 && + regulator_is_enabled(rockchip->vpcie0v9) > 0; + if (!IS_ERR(rockchip->vpcie12v)) { err = regulator_enable(rockchip->vpcie12v); if (err) { @@ -890,6 +909,9 @@ struct rockchip_pcie *rockchip = dev_get_drvdata(dev); int err; + /* The 0.9V supply was turned off on suspend, so Tpvperl applies. */ + rockchip->supplies_pre_enabled = false; + err = regulator_enable(rockchip->vpcie0v9); if (err) { dev_err(dev, "fail to enable vpcie0v9 regulator\n"); -- 2.43.0