From: sashiko-bot@kernel.org
To: "Zhanpeng Zhang" <zhangzhanpeng.jasper@bytedance.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v10 5/9] riscv: mm: avoid enabling interrupts for nofault page faults
Date: Fri, 11 Sep 2026 12:28:33 +0000 [thread overview]
Message-ID: <20260911122834.37A1C1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260911121456.33223-6-zhangzhanpeng.jasper@bytedance.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Premature exception fixup bypasses vmalloc_fault() on 32-bit RISC-V, breaking nofault accesses to valid vmalloc addresses.
--
commit cb75a61df5b372879cfe9c956e1ab3e4a9d62e0b
Author: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>
riscv: mm: avoid enabling interrupts for nofault page faults
This commit modifies the page fault handler on RISC-V to handle nofault
accesses and perform exception-table fixups before enabling interrupts or
running tracepoints. This keeps interrupts disabled during nofault accesses
from atomic contexts.
> diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
> index 04ed6f8acae4f..520495420462f 100644
> --- a/arch/riscv/mm/fault.c
> +++ b/arch/riscv/mm/fault.c
> @@ -294,6 +294,13 @@ void handle_page_fault(struct pt_regs *regs)
> if (kprobe_page_fault(regs, cause))
> return;
>
> + /*
> + * Nofault accesses must be resolved through the exception table before
> + * entering the generic fault path or enabling interrupts.
> + */
> + if (unlikely(faulthandler_disabled()) && fixup_exception(regs))
> + return;
> +
[Severity: High]
Does this early exception fixup bypass vmalloc fault synchronization on 32-bit
RISC-V?
On 32-bit RISC-V, valid nofault kernel memory accesses to vmalloc addresses
(such as those made by copy_from_kernel_nofault() via bpf_probe_read_kernel()
or /proc/kcore) rely on vmalloc_fault() to lazily synchronize the PGD.
Because copy_from_kernel_nofault() executes with pagefault_disable(),
faulthandler_disabled() evaluates to true. By intercepting this condition and
returning early, we completely bypass vmalloc_fault(), which is called slightly
later in handle_page_fault():
if ((!IS_ENABLED(CONFIG_MMU) || !IS_ENABLED(CONFIG_64BIT)) &&
unlikely(addr >= VMALLOC_START && addr < VMALLOC_END)) {
vmalloc_fault(regs, code, addr);
return;
}
Could this cause legitimate nofault accesses to valid vmalloc addresses to
spuriously fail with -EFAULT instead of completing successfully?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260911121456.33223-1-zhangzhanpeng.jasper@bytedance.com?part=5
next prev parent reply other threads:[~2026-09-11 12:28 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-11 12:14 [PATCH v10 0/9] riscv: add SBI Supervisor Software Events support Zhanpeng Zhang
2026-09-11 12:14 ` Zhanpeng Zhang
2026-09-11 12:14 ` [PATCH v10 1/9] riscv: add SBI SSE extension definitions Zhanpeng Zhang
2026-09-11 12:14 ` Zhanpeng Zhang
2026-09-11 12:20 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 2/9] riscv: add support for SBI Supervisor Software Events extension Zhanpeng Zhang
2026-09-11 12:14 ` Zhanpeng Zhang
2026-09-11 12:34 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 3/9] riscv: sse: mask events during shutdown and kexec Zhanpeng Zhang
2026-09-11 12:14 ` Zhanpeng Zhang
2026-09-11 12:30 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 4/9] drivers: firmware: add riscv SSE support Zhanpeng Zhang
2026-09-11 12:14 ` Zhanpeng Zhang
2026-09-11 12:35 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 5/9] riscv: mm: avoid enabling interrupts for nofault page faults Zhanpeng Zhang
2026-09-11 12:14 ` Zhanpeng Zhang
2026-09-11 12:28 ` sashiko-bot [this message]
2026-09-11 12:14 ` [PATCH v10 6/9] perf: RISC-V: support callchains with SSE delivery Zhanpeng Zhang
2026-09-11 12:14 ` Zhanpeng Zhang
2026-09-11 12:35 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 7/9] perf: RISC-V: add support for SSE event Zhanpeng Zhang
2026-09-11 12:14 ` Zhanpeng Zhang
2026-09-11 12:37 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 8/9] selftests/riscv: add SSE test module Zhanpeng Zhang
2026-09-11 12:14 ` Zhanpeng Zhang
2026-09-11 12:40 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 9/9] selftests/riscv: add perf user-stack SSE copy regression test Zhanpeng Zhang
2026-09-11 12:14 ` Zhanpeng Zhang
2026-09-11 12:33 ` sashiko-bot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260911122834.37A1C1F000FF@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
--cc=zhangzhanpeng.jasper@bytedance.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.