From: sashiko-bot@kernel.org
To: linux-kernel@vger.kernel.org, "Nuno Sá" <nuno.sa@analog.com>,
linux-mtd@lists.infradead.org
Cc: "Miquel Raynal" <miquel.raynal@bootlin.com>,
"Pratyush Yadav" <pratyush@kernel.org>,
"Michael Walle" <mwalle@kernel.org>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
"Takahiro Kuwano" <takahiro.kuwano@infineon.com>,
"Richard Weinberger" <richard@nod.at>
Subject: Re: [PATCH 2/2] mtd: spi-nor: issi: Add support for is25wx01g
Date: Fri, 11 Sep 2026 15:44:12 +0000 [thread overview]
Message-ID: <20260911154412.B53B01F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260911-mtd-spi-nor-new-issi-chip-v1-2-c54615f8c30f@analog.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The patch introduces multiple build failures due to an incomplete forward-port from an older kernel version. It references non-existent struct fields, uses an undeclared flag, and attempts an outdated method to disable 16-bit status register writes.
--
commit 2a2f93cf391e237e4b5b711cef68cc225e2bc2fe
Author: Nuno Sá <nuno.sa@analog.com>
mtd: spi-nor: issi: Add support for is25wx01g
This patch adds support for the ISSI IS25WX01G 1 Gbit octal NOR flash. It
relies on SFDP and provides BFPT fixups to handle the lack of a 35h command
and to disable the quad enable method.
> diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
> index 2f057d731df2a..aac9d19b90fcf 100644
> --- a/drivers/mtd/spi-nor/issi.c
> +++ b/drivers/mtd/spi-nor/issi.c
> @@ -29,6 +29,29 @@ static const struct spi_nor_fixups is25lp256_fixups = {
> .post_bfpt = is25lp256_post_bfpt_fixups,
> };
>
> +static int is25wx01g_post_bfpt_fixups(struct spi_nor *nor,
> + const struct sfdp_parameter_header *bfpt_header,
> + const struct sfdp_bfpt *bfpt)
> +{
> + /*
> + * There is no Status Register 2 and no 35h command. And WRITE STATUS
> + * REGISTER takes a single data byte.
> + */
> + nor->flags &= ~SNOR_F_HAS_16BIT_SR;
[Severity: Low]
Does this code compile on the target tree? struct spi_nor does not appear
to have a flags member in the current API, and SNOR_F_HAS_16BIT_SR seems
to be undeclared.
> +
> + /*
> + * The BFPT Quad Enable Requirement field is set to a reserved value, so
> + * spi_nor_parse_bfpt() leaves the quad enable method at its default.
> + * Make sure we disable it as there is no quad mode anyway.
> + */
> + nor->params->quad_enable = NULL;
> + return 0;
> +}
> +
> +static const struct spi_nor_fixups is25wx01g_fixups = {
> + .post_bfpt = is25wx01g_post_bfpt_fixups,
> +};
> +
[ ... ]
> @@ -120,6 +143,10 @@ static const struct flash_info issi_nor_parts[] = {
> .id = SNOR_ID(0x9d, 0x70, 0x19),
> .name = "is25wp256",
> .flags = SPI_NOR_QUAD_PP,
> + }, {
> + .id = SNOR_ID(0x9d, 0x5b, 0x1b),
> + .name = "is25wx01g",
> + .fixups = &is25wx01g_fixups,
[Severity: Low]
Does struct flash_info have a fixups member in the current framework?
It looks like fixups might need to be registered via struct
spi_nor_manufacturer and its fixups array instead.
> }
> };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260911-mtd-spi-nor-new-issi-chip-v1-0-c54615f8c30f@analog.com?part=2
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next prev parent reply other threads:[~2026-09-11 15:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-11 15:36 [PATCH 0/2] mtd: spi-nor: issi: add support for the IS25WX01G octal flash Nuno Sá
2026-09-11 15:36 ` [PATCH 1/2] mtd: spi-nor: sfdp: get the 1-1-8 and 1-8-8 page programs from 4BAIT Nuno Sá
2026-09-11 15:36 ` [PATCH 2/2] mtd: spi-nor: issi: Add support for is25wx01g Nuno Sá
2026-09-11 15:44 ` sashiko-bot [this message]
2026-09-11 16:09 ` Nuno Sá
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