From: Aurelien Jarno <aurelien@aurel32.net>
To: linux-kernel@vger.kernel.org, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Andy Chiu <andybnac@gmail.com>,
Conor Dooley <conor.dooley@microchip.com>,
linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE)
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: [PATCH] riscv: fix RVG_SYSTEM_CSR_MASK width mask
Date: Fri, 11 Sep 2026 21:42:33 +0200 [thread overview]
Message-ID: <20260911194233.3379532-1-aurelien@aurel32.net> (raw)
RVG_SYSTEM_CSR_MASK should be 12 bits [31:20], shifted down by 20 bits.
Replace GENMASK(12, 0) by GENMASK(11, 0).
Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
arch/riscv/include/asm/insn.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index c3005573e8c9..ad348d8b8857 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -142,7 +142,7 @@
#define RVG_OPCODE_JAL 0x6f
#define RVG_OPCODE_SYSTEM 0x73
#define RVG_SYSTEM_CSR_OFF 20
-#define RVG_SYSTEM_CSR_MASK GENMASK(12, 0)
+#define RVG_SYSTEM_CSR_MASK GENMASK(11, 0)
/* parts of opcode for RVF, RVD and RVQ */
#define RVFDQ_FL_FS_WIDTH_OFF 12
--
2.53.0
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next reply other threads:[~2026-09-11 19:42 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-11 19:42 Aurelien Jarno [this message]
2026-10-04 3:44 ` [PATCH] riscv: fix RVG_SYSTEM_CSR_MASK width mask Jisheng Zhang
2026-10-04 22:21 ` Paul Walmsley
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