From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B39E1326927 for ; Sat, 12 Sep 2026 14:42:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789224133; cv=none; b=JfA7+gn9GZkXI2Y2sxFw3Go48apm6026EGD8KM8Iqp5TVrbBci+bdiSiv9wjdLyPoIrLwf6EynKXZT/1JZMnFCpJSMmaVnNcShh6C3Dg/SoPJisEIjTSCX4JiABWg01rLaYlh8L2AmjhkJWvs7FYChm8ZxS3Z6OOdpq6J1+0b3E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789224133; c=relaxed/simple; bh=sURQb8tdKvvw4fnI72LpaSDoTJ7Ex1zGJW8/tGmZAJU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Qw0WkCDiRIauRw9A2yd9K/JufF0mLgaoC5/fJrwIlDMJBSHcX5kmVAovTrhiv62tm+DcCudXWWM8oCoa0Lcpf9CDxfNhM3xZlpSQaRIOigiBYEOwRQOPzTE9fh1B2zqWWV+SzWPv1QSqxu3GMIaOlU9RVX12gHzUddQmRK4rIWg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JLV457jh; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JLV457jh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1C1841F00898; Sat, 12 Sep 2026 14:42:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1789224132; bh=G7lXBrNPWmIwKyzNHBz0XqmkPFeVjSS49X7drfF3Ad4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=JLV457jhjSj2AGPhG7lDkRrkQ2vvH7RRKZviQAw4x2lXicZYQZuHpFbnIHaHJmmE3 hWSXwf5TBR5uxD8OBImzcWb0zoHjWbVQxhe4npByH1tUjvt8es+ziIufouKZLIRohL n5WFcBVTpQfFtfxPfoVGKHsq72jMfWyfbrzUcLNAa3QM0f6pN6aJwADe8hQ4O0APMk qrbMpj4r0HQWKKSMpf+zmKL7PTOyv8XENLNOZCmbdfZIM4d/G53J8lG0sbOHsnUz8M 0BcbIDal2uFPDPgcygSziOF4qqfWvJ+tGH3DzBMckz2cSj9PkpHZqtaFhcmK9LGVUK mQFXgNXOwFrdQ== From: Sasha Levin To: stable@vger.kernel.org Cc: Heikki Krogerus , Rodrigo Vivi , Sasha Levin Subject: [PATCH 7.2.y 3/3] drm/xe/i2c: Keep the i2c controller always enabled Date: Sat, 12 Sep 2026 10:42:08 -0400 Message-ID: <20260912144208.2989900-3-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260912144208.2989900-1-sashal@kernel.org> References: <2026090957-lilac-mocha-69d6@gregkh> <20260912144208.2989900-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Heikki Krogerus [ Upstream commit 244abef7f280a6a84297bfab5fd2e77147bc419a ] Some platforms make an assumption that the i2c controller's enabled state indicates also the power state of the controller. This can create a problem when the controller is in disabled state, because the hardware may assume incorrectly that it is then also in low-power state. To fix this, the controller is kept enabled by taking over the IC_ENABLE register. The controller has to be disabled when the configuration is updated and when the target address or the slave address are assigned, so disabling it when IC_CON, IC_TAR or IC_SAR registers are programmed, and then re-enabling it again. Fixes: f0e53aadd702 ("drm/xe: Support for I2C attached MCUs") Cc: stable@vger.kernel.org Signed-off-by: Heikki Krogerus Reviewed-by: Rodrigo Vivi Link: https://patch.msgid.link/20260811121008.1493015-4-heikki.krogerus@linux.intel.com Signed-off-by: Rodrigo Vivi (cherry picked from commit 76cc14e2faed1adae20f4ee144ead0e3a7566c49) Signed-off-by: Rodrigo Vivi [ adapted xe_i2c_write() to the older callback structure without SMBus-alert handling. ] Signed-off-by: Sasha Levin --- drivers/gpu/drm/xe/regs/xe_i2c_regs.h | 2 + drivers/gpu/drm/xe/xe_i2c.c | 57 ++++++++++++++++++++++++++- drivers/gpu/drm/xe/xe_i2c.h | 1 + 3 files changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_i2c_regs.h b/drivers/gpu/drm/xe/regs/xe_i2c_regs.h index f2e455e2bfe45..37550e4a20f80 100644 --- a/drivers/gpu/drm/xe/regs/xe_i2c_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_i2c_regs.h @@ -20,4 +20,6 @@ #define I2C_CONFIG_CMD XE_REG(I2C_CONFIG_SPACE_OFFSET + PCI_COMMAND) #define I2C_CONFIG_PMCSR XE_REG(I2C_CONFIG_SPACE_OFFSET + 0x84) +#define I2C_REG(reg) XE_REG((reg) + I2C_MEM_SPACE_OFFSET) + #endif /* _XE_I2C_REGS_H_ */ diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c index f05f23221c1b7..21ed8f5e2499d 100644 --- a/drivers/gpu/drm/xe/xe_i2c.c +++ b/drivers/gpu/drm/xe/xe_i2c.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,8 @@ #include #include +#include + #include "regs/xe_i2c_regs.h" #include "regs/xe_irq_regs.h" @@ -254,11 +257,40 @@ static void xe_i2c_remove_irq(struct xe_i2c *i2c) irq_domain_remove(i2c->irqdomain); } +/* See "Disabling DW_apb_i2c" in the DesignWare DW_abp_i2c databook. */ +static void xe_i2c_disable(struct xe_i2c *i2c) +{ + int timeout = 100; + u32 status; + + xe_mmio_rmw32(i2c->mmio, I2C_REG(DW_IC_ENABLE), DW_IC_ENABLE_ENABLE, 0); + + do { + status = xe_mmio_read32(i2c->mmio, I2C_REG(DW_IC_ENABLE_STATUS)); + if (!(status & DW_IC_ENABLE_ENABLE)) + return; + /* Can't sleep here. */ + udelay(25); + } while (timeout--); + + dev_warn(i2c->drm_dev, "timeout in disabling i2c adapter\n"); +} + static int xe_i2c_read(void *context, unsigned int reg, unsigned int *val) { struct xe_i2c *i2c = context; - *val = xe_mmio_read32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET)); + *val = xe_mmio_read32(i2c->mmio, I2C_REG(reg)); + + switch (reg) { + case DW_IC_ENABLE: + case DW_IC_ENABLE_STATUS: + FIELD_MODIFY(DW_IC_ENABLE_ENABLE, val, + i2c->ic_enable & DW_IC_ENABLE_ENABLE); + break; + default: + break; + } return 0; } @@ -267,8 +299,29 @@ static int xe_i2c_write(void *context, unsigned int reg, unsigned int val) { struct xe_i2c *i2c = context; - xe_mmio_write32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET), val); + switch (reg) { + case DW_IC_CON: + case DW_IC_TAR: + case DW_IC_SAR: + /* Disable the controller. */ + xe_i2c_disable(i2c); + + /* Write the register. */ + xe_mmio_write32(i2c->mmio, I2C_REG(reg), val); + + /* Enable the controller. */ + xe_mmio_rmw32(i2c->mmio, I2C_REG(DW_IC_ENABLE), 0, DW_IC_ENABLE_ENABLE); + return 0; + case DW_IC_ENABLE: + i2c->ic_enable = val; + /* Other fields can be updated except the enable bit. */ + val |= DW_IC_ENABLE_ENABLE; + break; + default: + break; + } + xe_mmio_write32(i2c->mmio, I2C_REG(reg), val); return 0; } diff --git a/drivers/gpu/drm/xe/xe_i2c.h b/drivers/gpu/drm/xe/xe_i2c.h index 425d8160835f4..68124617f2bf9 100644 --- a/drivers/gpu/drm/xe/xe_i2c.h +++ b/drivers/gpu/drm/xe/xe_i2c.h @@ -34,6 +34,7 @@ struct xe_i2c { struct platform_device *pdev; struct i2c_adapter *adapter; struct i2c_client *client[XE_I2C_MAX_CLIENTS]; + unsigned int ic_enable; struct notifier_block bus_notifier; struct work_struct work; -- 2.53.0