From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
"Pierrick Bouvier" <pierrick.bouvier@oss.qualcomm.com>,
"Brian Cain" <brian.cain@oss.qualcomm.com>,
marco.liebel@oss.qualcomm.com, "Helge Deller" <deller@gmx.de>,
"Paolo Bonzini" <pbonzini@redhat.com>,
richard.henderson@linaro.org,
"Laurent Vivier" <laurent@vivier.eu>
Subject: [PATCH v3 0/6] hexagon: Add HVX context
Date: Sun, 13 Sep 2026 08:59:22 -0700 [thread overview]
Message-ID: <20260913155928.365928-1-brian.cain@oss.qualcomm.com> (raw)
Add HVX contexts to Hexagon translation, necessary for system emulation.
Change the HVX instruction translation to access the context via a base
pointer.
Modeling the HVX context mapping while avoiding the need to copy the
context when the OS scheduler decides to remap them required some general
TCG gvec changes to enable some more _var forms.
In v3:
- fixed HVX context alignment declarations
- created hex_hvx_ptr global for sysemu, abstraction hex_hvx() to refer
to the context.
- added some test cases (reset Marco's R-b)
In v2:
- Removed unused default hvx context from target/hexagon/cpu.[ch], add a
hexagon_hvx_select_context() to the reset instead.
- combined the HVX pointer, QOM context, and SSR:XA selection work commits
into `share HVX contexts among CPUs`.
v2: https://lore.kernel.org/qemu-devel/20260911204334.1264922-1-brian.cain@oss.qualcomm.com/
v1: https://lore.kernel.org/qemu-devel/20260910153221.1674285-1-brian.cain@oss.qualcomm.com/
Brian Cain (6):
tcg: split out _var forms of gvec logical, abs and min/max ops
tcg: add base arguments to the gvec 2s, dup_i32 and cmp expanders
tcg: split out _var forms of gvec saturating/mul/shift-immediate ops
target/hexagon: raise an exception for HVX with SSR:XE clear
target/hexagon: share HVX contexts among CPUs
tests/functional/hexagon: add HVX tests
include/hw/hexagon/hexagon.h | 1 +
include/hw/hexagon/hexagon_hvx_context.h | 27 +
include/tcg/tcg-op-gvec-common.h | 97 +++
target/hexagon/cpu.h | 28 +-
target/hexagon/cpu_helper.h | 1 +
target/hexagon/gen_tcg_hvx.h | 608 ++++++++++---------
target/hexagon/genptr.h | 8 +
target/hexagon/mmvec/macros.h | 14 +-
target/hexagon/translate.h | 14 +-
hw/hexagon/hex-subsys.c | 36 ++
hw/hexagon/hexagon_hvx_context.c | 84 +++
linux-user/main.c | 3 +
target/hexagon/cpu.c | 32 +-
target/hexagon/cpu_helper.c | 72 +++
target/hexagon/gdbstub.c | 16 +-
target/hexagon/genptr.c | 102 ++--
target/hexagon/machine.c | 12 +
target/hexagon/op_helper.c | 37 +-
target/hexagon/translate.c | 71 ++-
tcg/tcg-op-gvec.c | 617 ++++++++++++++------
hw/hexagon/meson.build | 1 +
target/hexagon/hex_common.py | 179 +++---
tests/functional/hexagon/test_arch_tests.py | 7 +
tests/functional/hexagon/test_systests.py | 6 +
24 files changed, 1451 insertions(+), 622 deletions(-)
create mode 100644 include/hw/hexagon/hexagon_hvx_context.h
create mode 100644 hw/hexagon/hexagon_hvx_context.c
--
2.34.1
next reply other threads:[~2026-09-13 16:01 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-13 15:59 Brian Cain [this message]
2026-09-13 15:59 ` [PATCH v3 1/6] tcg: split out _var forms of gvec logical, abs and min/max ops Brian Cain
2026-09-13 15:59 ` [PATCH v3 2/6] tcg: add base arguments to the gvec 2s, dup_i32 and cmp expanders Brian Cain
2026-09-13 15:59 ` [PATCH v3 3/6] tcg: split out _var forms of gvec saturating/mul/shift-immediate ops Brian Cain
2026-09-13 15:59 ` [PATCH v3 4/6] target/hexagon: raise an exception for HVX with SSR:XE clear Brian Cain
2026-09-13 15:59 ` [PATCH v3 5/6] target/hexagon: share HVX contexts among CPUs Brian Cain
2026-09-13 22:02 ` Richard Henderson
2026-09-13 15:59 ` [PATCH v3 6/6] tests/functional/hexagon: add HVX tests Brian Cain
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