Re: [PATCH v4 1/2] arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The patch introduces an inconsistency in the SoC device tree by adding the `compatible = "pciclass,0604";` string only to `pcieport0` and omitting it for the identical secondary root port `pcieport1`.
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commit af4d1e90e3b54337cb2c17a523874c97e4e2e7af
Author: Wei Deng <wei.deng@oss.qualcomm.com>

arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port

This commit adds the compatible string pciclass,0604 to the pcieport0 node in
monaco.dtsi. This allows the PCI subsystem to associate the DT node with the
PCI-to-PCI bridge device, enabling downstream DT nodes to be matched to PCI
devices.

> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index cfe39f923224f..e18b3ed54cd9e 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -2394,6 +2394,7 @@ opp-32000000 {
>  			};
>  
>  			pcieport0: pcie@0 {
> +				compatible = "pciclass,0604";

[Severity: Medium]
Should this compatible string also be added to pcieport1?

Looking at the device tree in arch/arm64/boot/dts/qcom/monaco.dtsi, there is an
identical secondary root port that misses this update:

			pcieport1: pcie@0 {
				device_type = "pci";
				reg = <0x0 0x0 0x0 0x0 0x0>;
				bus-range = <0x01 0xff>;

If a board design utilizes pcieport1 and adds a downstream endpoint, wouldn't it
fail to associate the DT node with the PCI-to-PCI bridge device in the same way?

>  				device_type = "pci";
>  				reg = <0x0 0x0 0x0 0x0 0x0>;
>  				bus-range = <0x01 0xff>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260914-b4-monaco-evk-m2-v1-v4-0-dab83b048d03@oss.qualcomm.com?part=1