Re: [PATCH v2 01/13] arm64: Add ESR fault helpers

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Generic ESR helpers `esr_trap_is_iabt()` and `esr_abt_is_exec_fault()` silently ignore instruction aborts from the current Exception level (`ESR_ELx_EC_IABT_CUR`).
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commit 5b92bb137f8d48a92e83b6486d7d57faacb410df
Author: Lorenzo Stoakes (ARM) <ljs@kernel.org>

arm64: Add ESR fault helpers

This commit adds helper functions that operate directly on ESR values, mirroring
equivalent KVM vCPU wrappers to allow KVM's stage-2 fault handling to operate
on plain ESR values.

> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
> index f816f5d77f1a5..9c0205983d9a8 100644
> --- a/arch/arm64/include/asm/esr.h
> +++ b/arch/arm64/include/asm/esr.h
> @@ -437,6 +437,50 @@
>  #ifndef __ASSEMBLER__
>  #include <asm/types.h>
>  
> +static __always_inline u8 esr_get_ec(unsigned long esr)
> +{
> +	return ESR_ELx_EC(esr);
> +}
> +
> +static __always_inline bool esr_trap_is_iabt(unsigned long esr)
> +{
> +	return esr_get_ec(esr) == ESR_ELx_EC_IABT_LOW;
> +}

[Severity: Low]
Does this intentionally ignore instruction aborts originating from the current
Exception level (ESR_ELx_EC_IABT_CUR)?

While this is safe for the current KVM stage-2 fault handling which only
processes LOW traps, moving this to a generic architectural header with a
generic name introduces a trap for future callers evaluating host kernel
page faults. It also contrasts with esr_is_data_abort() in the same file,
which correctly checks both LOW and CUR variants.

[ ... ]

> +static __always_inline bool esr_abt_is_exec_fault(unsigned long esr)
> +{
> +	return esr_trap_is_iabt(esr) && !esr_abt_is_s1ptw(esr);
> +}

[Severity: Low]
Because this relies on esr_trap_is_iabt(), does this mean it will also
misclassify current-EL execution faults?

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20260914-kvm-arm-prefault-v2-0-26fb47f74b73@kernel.org?part=1