Re: [PATCH net-next v8 09/15] dpll: sit9531x: implement output pin state on a DPLL

[Ali Rouhi <arouhi@sitime.com>]

Replies inline.

> does the banner describe the wrong polarity?  It says MASK+STATE are set to
> mute, while the body sets MASK and clears STATE

Fixed in v9 -- the banner now says "sets MASK and clears STATE",
matching the register description and the code.

> Can a partial register sequence here leave sitdev->out[index].enabled
> permanently disagreeing with the hardware?

v9 re-reads the force/state pair after a failed
sequence and records what the hardware actually holds, so the cached flag
cannot disagree with the chip for the life of the binding.

> Does this read past sitdev->out[] for the internal INTSYNC source pin?

Resolved by the v9 registration restructure: the
INTSYNC source pin is registered only together with its dedicated ops table
(the inter-PLL sync patch), so no commit dispatches it to the generic output
getter and the out-of-bounds read is gone at every bisect point.