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[204.195.96.226]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cc4f6aa2767sm2654901a12.1.2026.09.15.06.20.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 06:20:30 -0700 (PDT) Date: Tue, 15 Sep 2026 06:20:23 -0700 From: Stephen Hemminger To: Mattias =?UTF-8?B?UsO2bm5ibG9t?= Cc: , Mattias =?UTF-8?B?UsO2bm5ibG9t?= Subject: Re: [RFC 1/1] eal/x86: replace inline assembly prefetch with cc builtins Message-ID: <20260915062023.76099932@phoenix.local> In-Reply-To: <20250223125215.358925-2-mattias.ronnblom@ericsson.com> References: <20250223125215.358925-1-mattias.ronnblom@ericsson.com> <20250223125215.358925-2-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Sun, 23 Feb 2025 13:52:15 +0100 Mattias R=C3=B6nnblom wrote: > Implement the 32- and 64-bit x86 rte_prefetch() functions and > rte_prefetch_non_temporal() using compiler builtins, rather than > inline assembly. >=20 > This change frees the compiler to do certain optimizations that > otherwise wouldn't be possible. >=20 > Signed-off-by: Mattias R=C3=B6nnblom > --- I like this getting rid of asm is good. AI review did spot some things worth addressing, I don't think benchmarking is needed. But moving to arch neutral file is good idea. Subject: Re: [RFC 1/1] eal/x86: replace inline assembly prefetch with cc bu= iltins The patch still applies cleanly to main. Codegen checked with gcc 13 at -O0 and -O2, x86_64 and -m32: locality 3/2/1/0 emits prefetcht0/t1/t2/nta, identical to the current inline asm. Worth resending as a non-RFC after the items below. Warning The comment in rte_prefetch_non_temporal() is a copy/paste leftover. It says "1 sets target cache level to L3" but the call passes 0, which GCC maps to prefetchnta. The same four-line comment is repeated in every function. The locality argument is also not a cache level; the mapping to prefetcht0/t1/t2/nta is the x86 backend's choice. Replace with a single comment above rte_prefetch0(), e.g.: /* * On x86, __builtin_prefetch() read hints with locality 3, 2, 1, 0 * generate prefetcht0, prefetcht1, prefetcht2 and prefetchnta. */ The commit message says the change "frees the compiler to do certain optimizations" without naming them. Say what inline asm blocks (it is opaque to the optimizer; the pointer must be materialized and loops containing it do not vectorize) and include either a codegen example or benchmark numbers. Also state that the generated instruction is unchanged. Info With this change the non-MSVC x86 code is the same as lib/eal/loongarch/include/rte_prefetch.h. Consider providing the __builtin_prefetch() versions in generic/rte_prefetch.h and letting arch headers override only where needed (MSVC, arm, ppc). That drops duplicate code in two arch headers. Unlike the asm, __builtin_prefetch() emits nothing on 32-bit x86 when SSE is not enabled (e.g. -march=3Di686). Not a problem for DPDK builds given the SSE4.2 baseline, but applications compiling the headers with their own flags would silently lose the prefetch.