From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
To: Rosen Penev <rosenp@gmail.com>
Cc: linux-gpio@vger.kernel.org, Linus Walleij <linusw@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>,
Clark Williams <clrkwllms@kernel.org>,
Steven Rostedt <rostedt@goodmis.org>,
open list <linux-kernel@vger.kernel.org>,
"open list:Real-time Linux (PREEMPT_RT):Keyword:PREEMPT_RT"
<linux-rt-devel@lists.linux.dev>
Subject: Re: [PATCHv2] gpio: mvebu: keep resume masks within the irqchip cache
Date: Tue, 15 Sep 2026 08:43:52 +0200 [thread overview]
Message-ID: <20260915064352.T4HiPnt_@linutronix.de> (raw)
In-Reply-To: <20260915004406.115230-1-rosenp@gmail.com>
On 2026-09-14 17:44:06 [-0700], Rosen Penev wrote:
> mvebu_gpio_resume() writes the edge/level mask registers saved at
> suspend time straight back to hardware, bypassing the irqchip's
> mask_cache_priv. genirq skips mask_irq() for a line it already
> considers masked, so restoring a bit in hardware that genirq thinks
> is still masked leaves that line unmasked behind genirq's back. An
> asserted level line then has nobody to ack it, and the moment
> interrupts are re-enabled the chained handler storms, hanging resume.
Why is the mask value changed after suspend?
Sebastian
next prev parent reply other threads:[~2026-09-15 6:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 0:44 [PATCHv2] gpio: mvebu: keep resume masks within the irqchip cache Rosen Penev
2026-09-15 0:57 ` sashiko-bot
2026-09-15 6:43 ` Sebastian Andrzej Siewior [this message]
2026-09-15 22:24 ` Rosen Penev
2026-09-16 6:55 ` Sebastian Andrzej Siewior
2026-09-17 9:52 ` Bartosz Golaszewski
2026-09-17 10:04 ` Sebastian Andrzej Siewior
2026-09-17 23:14 ` Rosen Penev
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