[PATCH i-g-t] tests/kms_cursor_legacy: Skip timing checks in simulation to avoid false negatives

[Jeevan B <jeevan.b@intel.com>]

Simulation environments often do not reflect real hardware timing
accurately, which can result in false negatives during the
flip-vs-cursor-busy-crc vblank and CRC checks. To prevent such issues,
this patch conditionally skips these timing validations when the test
runs in simulation.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_cursor_legacy.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/tests/kms_cursor_legacy.c b/tests/kms_cursor_legacy.c
index 62339855e..810c593f5 100644
--- a/tests/kms_cursor_legacy.c
+++ b/tests/kms_cursor_legacy.c
@@ -1775,8 +1775,10 @@ static void flip_vs_cursor_busy_crc(igt_display_t *display, bool atomic)
 		flip_nonblocking(display, crtc, atomic, &fb_info[1], NULL);
 		do_ioctl(display->drm_fd, DRM_IOCTL_MODE_CURSOR, &arg[i]);
 
-		igt_assert_eq(igt_crtc_get_vblank(crtc, 0),
-			      vblank_start);
+		/* Simulation ioctl latency can exceed a vblank period even without a real miss. */
+		if (!igt_run_in_simulation())
+			igt_assert_eq(igt_crtc_get_vblank(crtc, 0),
+				      vblank_start);
 
 		igt_pipe_crc_get_current(display->drm_fd, pipe_crc, &test_crc);
 
@@ -1792,7 +1794,11 @@ static void flip_vs_cursor_busy_crc(igt_display_t *display, bool atomic)
 		igt_plane_set_fb(plane_primary, &fb_info[0]);
 		igt_display_commit2(display, COMMIT_UNIVERSAL);
 
-		igt_assert_crc_equal(&crcs[i], &test_crc);
+		/* Simulation timing can shift when the busy CRC is sampled, causing a false mismatch. */
+		if (!igt_run_in_simulation())
+			igt_assert_crc_equal(&crcs[i], &test_crc);
+		else if (!igt_check_crc_equal(&crcs[i], &test_crc))
+			igt_info("CRC mismatch ignored on simulation for i=%d\n", i);
 	}
 
 	igt_pipe_crc_stop(pipe_crc);
-- 
2.43.0