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[80.230.79.236]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49e7d6a9d1dsm78981575e9.10.2026.09.15.07.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 07:22:57 -0700 (PDT) Date: Tue, 15 Sep 2026 10:22:54 -0400 From: "Michael S. Tsirkin" To: David Vrabel Cc: =?iso-8859-1?Q?C=E9dric?= Le Goater , qemu-devel@nongnu.org, Alex Williamson , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Zhao Liu Subject: Re: [PATCH 0/2] hw/pci-bridge: Add x-speed and x-width properties to xio3130 ports Message-ID: <20260915102221-mutt-send-email-mst@kernel.org> References: <20260915072507.1230187-1-clg@redhat.com> <20260915060015-mutt-send-email-mst@kernel.org> <81c899d9-a9fb-4eb2-ad85-7dde2f626646@nutanix.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <81c899d9-a9fb-4eb2-ad85-7dde2f626646@nutanix.com> Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Sep 15, 2026 at 12:17:31PM +0100, David Vrabel wrote: > On 15/09/2026 11:01, Michael S. Tsirkin wrote: > > > > On Tue, Sep 15, 2026 at 09:25:05AM +0200, Cédric Le Goater wrote: > > > Hello, > > > > > > The xio3130-downstream and x3130-upstream devices lacks x-speed and > > > x-width device properties, making it impossible to configure PCIe link > > > speed/width when building PIX switch topologies for GPU/NIC passthrough. > > > > > > Fix that and preserve migration compatibility with a 2.5GT/s x1 default. > > > > > > Thanks, > > > > > > C. > > > > Given they are clearly intended for users, time to rename to width/speed > > everywhere? > > A more comprehensive series (hw/pci-bridge: Configurable apparent bandwidth > for the PCIe topology) is here: > > https://patchew.org/QEMU/20260908155223.164787-1-david.vrabel@nutanix.com/ > > This adds new upstream and switch port devices with configurable speed/width > and renames the options so they are non-experimental (but do not the open > question about the usability of the speed option with the need to set 2.5 > GT/s as the string "2_5"). > > I did consider adding options to the XIO3130 device but since the real > hardware is Gen 1 only and does not support speeds/widths other 2.5GT/s/1x I > didn't consider it appropriate to claim these emulated ports are more > capable than the real hardware. > > David Right that makes more sense to me. Cédric what do you think? -- MST