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From: sashiko-bot@kernel.org
To: "Amin Gattout" <amin.gattout@gmail.com>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org,
	media-ci@linuxtv.org
Subject: Re: [PATCH v2 2/2] arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3576
Date: Tue, 15 Sep 2026 12:06:20 +0000	[thread overview]
Message-ID: <20260915120620.EC8DE1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260915-csi-2-rcv-dts-v2-2-bdaf8141616a@gmail.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dts: rockchip: rk3576: unresolved phandles to csi_dphy0 and csi_dphy1
--

commit 74283d225fb35bb3bcff8713830fbb589c7d7648
Author: Amin Gattout <amin.gattout@gmail.com>

arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3576

This commit adds MIPI CSI-2 receiver nodes for MIPI1 and MIPI3 units to the
RK3576 device tree. It omits the remaining units because MIPI DCPHY and
split DPHY modes are not yet supported.

> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> index b0c0d3c8b1b14..adec5c762673b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> @@ -1314,6 +1314,58 @@ vdec_mmu: iommu@27b00800 {
[ ... ]
> +		csi1: csi@27c90000 {
> +			compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2";
> +			reg = <0x0 0x27c90000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "err1", "err2";
> +			clocks = <&cru PCLK_CSI_HOST_1>;
> +			phys = <&csi_dphy0>;

[Severity: Low]
Does this introduce an undefined phandle reference to csi_dphy0?

The label csi_dphy0 does not appear to be defined anywhere in rk3576.dtsi or
its included files, which causes a dtc build failure with a reference to
non-existent node or label error during make dtbs.

> +			power-domains = <&power RK3576_PD_VI>;
> +			resets = <&cru SRST_P_CSI_HOST_1>;
> +			status = "disabled";
[ ... ]
> +		csi3: csi@27cb0000 {
> +			compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2";
> +			reg = <0x0 0x27cb0000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "err1", "err2";
> +			clocks = <&cru PCLK_CSI_HOST_3>;
> +			phys = <&csi_dphy1>;

[Severity: Low]
Does this introduce an undefined phandle reference to csi_dphy1?

Similar to csi_dphy0 above, the label csi_dphy1 is missing from the device
tree sources, causing dtc to fail with an unresolved reference when building
the device tree binaries.

> +			power-domains = <&power RK3576_PD_VI>;
> +			resets = <&cru SRST_P_CSI_HOST_3>;
> +			status = "disabled";

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915-csi-2-rcv-dts-v2-0-bdaf8141616a@gmail.com?part=2

  reply	other threads:[~2026-09-15 12:06 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-15 11:56 [PATCH v2 0/2] Add MIPI CSI-2 receiver support for RK3576 Amin Gattout
2026-09-15 11:56 ` Amin Gattout
2026-09-15 11:56 ` [PATCH v2 1/2] media: dt-bindings: rockchip,rk3568-mipi-csi2: add rk3576 compatible Amin Gattout
2026-09-15 11:56   ` Amin Gattout
2026-09-15 11:56 ` [PATCH v2 2/2] arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3576 Amin Gattout
2026-09-15 11:56   ` Amin Gattout
2026-09-15 12:06   ` sashiko-bot [this message]
2026-10-05 19:06 ` (subset) [PATCH v2 0/2] Add MIPI CSI-2 receiver support for RK3576 Heiko Stuebner
2026-10-05 19:06   ` Heiko Stuebner

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