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([43.135.169.42]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33bf11e6af6sm1299889eec.3.2026.09.15.06.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 06:05:15 -0700 (PDT) From: NoNine X-Google-Original-From: NoNine To: suzuki.poulose@arm.com Cc: mike.leach@linaro.org, james.clark@linaro.org, alexander.shishkin@linux.intel.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Min Chen Subject: [PATCH 0/1] coresight: tmc-etr: Sync the trace buffer for the device Date: Tue, 15 Sep 2026 21:05:02 +0800 Message-ID: <20260915130503.645953-1-min.chen@siengine.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260915_060518_719332_F31025F8 X-CRM114-Status: GOOD ( 13.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Min Chen The flat ETR trace buffer is allocated with dma_alloc_noncoherent(), which reaches dma_alloc_pages(). That API zeroes the buffer with CPU stores and requires the caller to sync the memory for the device before the device writes into it. The TMC driver only ever syncs for the CPU afterwards, so a non-coherent sink is handed a buffer whose zero fill is still dirty in cache. On an AD1000 EVB this shows up as 64-byte-aligned runs of all-zero formatter frames in the first window of a freshly allocated buffer (1,100-2,400 runs in the leading ~4 MiB; later windows and reused buffers are clean). Writing a known pattern over the buffer before the arm and cleaning it removes every run, which pins the loss to the buffer hand-over. The ETR node is not marked dma-coherent. The patch adds a sync_for_device() buffer operation, implemented by the flat buffer, and calls it from __tmc_etr_enable_hw() before the TMC is enabled. It is intentionally flat-only: the ETR_SG and CATU data pages are allocated and immediately dma_map_page()d, so the map performs the architecture's for-device maintenance for the first hand-over. Their one remaining corner case - a barrier packet written into a full buffer before a live drain re-arms the same buffer - has no reproducer here and is left out. Tested on the AD1000 EVB: five first windows on freshly allocated buffers, including the first capture of a boot, carry no all-zero-frame runs and show the ordinary clean-stream profile (2.851% zero bytes), against 1,141-2,360 runs for the same measurement without the change. The patch was rebased onto the Coresight for-next/queue tip 5442d22da7db and builds with arm64 defconfig (Image and modules, no warnings or errors). The hardware run used the vendor 6.6.87 tree; the rebase carries the same change. Min Chen (1): coresight: tmc-etr: Sync the trace buffer for the device .../hwtracing/coresight/coresight-tmc-etr.c | 29 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 1 + 2 files changed, 30 insertions(+) -- 2.34.1