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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HzElr28T" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EB10A1F000FF; Tue, 15 Sep 2026 15:42:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1789486965; bh=AX4ZPiwoECjWJdEGXj/MDeda6bu8zZxZKkmx2AN2TIw=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=HzElr28TA2A6t61nW10Ne++osJPTsbGCzMP8PxZf9TkC22tkHny0PUmSm0mrtYt5E qHrRn7WdlXIwcaCevu0vhmJGc+5VykOc8MyhsU3XyFKth17SAel0jzGLEJj6ZG8exv /dNFWFRK3elx2rM9FqC73f5K9JBOG4DNgGL29T/IPLaTxkzC+IL5JwnCI0nkOuPO4e zAtvJN5aXHAGjeJjLmxFi0NOmpAXGv7p96FCR1EezQID5mW02/o/czyqNEWziabbOU qyanKfDkT2ppY+LZY0QS/AVpCJgusZrkbj+QMH2qqle12F2WMC1p1HI5yr1bJ+fbRS JWwThRNRNl+Fw== From: sashiko-bot@kernel.org Subject: Re: [PATCH v4 15/20] drm/bridge: starfive: Add JH7110 HDMI controller driver Reply-To: sashiko-reviews@lists.linux.dev To: "Michal Wilczynski" Cc: olteanv@gmail.com, robh@kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, lee@kernel.org, neil.armstrong@linaro.org, conor+dt@kernel.org, mfd@lists.linux.dev, linux-phy@lists.infradead.org, vkoul@kernel.org In-Reply-To: <20260915-jh7110-clean-send-v4-15-f0e4fd6f2cc8@samsung.com> References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> <20260915-jh7110-clean-send-v4-15-f0e4fd6f2cc8@samsung.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Tue, 15 Sep 2026 15:42:43 +0000 Message-Id: <20260915154243.EB10A1F000FF@smtp.kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: > Add the HDMI controller (bridge) driver for the StarFive JH7110. >=20 > This driver binds to the starfive,jh7110-inno-hdmi-controller node. It > gets its register access, module and bus clocks from voutcrg, and > consumes the pixel clock and the PHY from its hdmi_phy sibling. >=20 > The driver calls the generic inno_hdmi_probe function, which picks up > the regmap shared with the PHY from the parent device and registers a > DRM bridge. The .enable hook is responsible for setting the PHY's pixel > clock rate via clk_set_rate() and powering on the PHY via > phy_power_on(). >=20 > The DC8200 has two panels, each exposing a DP and a DPI interface, and a > mux in the video output system controller picks which of them drives the > HDMI transmitter. It comes out of reset on panel 0 / DPI, which happens > [ ... ] > devm_drm_bridge_add(). Releasing them in .remove runs before devres > unwinds and would leave the bridge registered with its clocks already > gated. >=20 > Signed-off-by: Michal Wilczynski Sashiko has reviewed this patch and found no issues. It looks great! --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260915-jh7110-cle= an-send-v4-0-f0e4fd6f2cc8@samsung.com?part=3D15