From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6F23C88E7F for ; Tue, 15 Sep 2026 15:46:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: References:In-Reply-To:Cc:To:Subject:From:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KG8tfa0h6EKXYdLayv4t2vselrXtPCzMrSP/6wXevBM=; b=AXkvBAAbSjRJHF xnoMCWX9ILk/bmdp//YNut50U00xEBxOVRg9W8tCzWT/KInZUQ1O3cQ8qwN8JnqhMlzFruxm3kG/s +jrTLjo59ARzMB+GKcJcB+XkFK4CTnRP3zPTq9dkph4C/2t8dvvPCPfCU+CjHeOXCYmtKu5vuAXRn APp5luZXlHuSsgt+30B9mtG09mMTgP/hDF8lRAD92hbelogN04UI11yVWONW7igdadmUuO60Y7WqC VyUI/3XIY3zHi3si8VlU7ekL/k6XmldcQH2vTMRqlobhWLIV7kl6lrW6hgG/sd97M2XPo9guE4YIe u9AxTkuRwTQbhWbZ5QOA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1x6VMQ-00000007HGS-28SJ; Tue, 15 Sep 2026 15:46:18 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1x6VMP-00000007HGE-4BIe for linux-phy@lists.infradead.org; Tue, 15 Sep 2026 15:46:18 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id 6FA93600C8; Tue, 15 Sep 2026 15:46:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1D171F000FF; Tue, 15 Sep 2026 15:46:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1789487177; bh=mjVSAPDqPKP4DItjJf1WRLNRKD0I+SD0o8c0mchPH3U=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=Vi7apQxczYynDIBLO65dXI6QHAkCcrqLXH7OW3PXQzj8b4GDy1gviRnGjulpMMVVn AZ/9GNPdOqaM2D1vtzBdQbmYT29IYJwGKXADhSbIctOOK965blDkGfZ4RS4GQ7h2nL FB06xbZC/q2U2zsS7irF4MgdsSTw/+1pfPBjVI3fxFTWCPo8eRnMeOSjkDcHpcoX3n zb/4U5V1bcEK6yM4NpezS9bCd5pPyVzCJKXfR/sKo6CGCT9b2zvyQBzg8dmzLKPL4N cHwuEg5FDmZqYwFcQfkj153q2TE/rhTDkp7T1/l2qXOUizc1gAFPA+Zlutrtjhn78e lIkvx1zC3teKg== From: sashiko-bot@kernel.org Subject: Re: [PATCH v4 18/20] phy: starfive: Add jh7110-inno-hdmi-phy driver To: "Michal Wilczynski" Cc: vkoul@kernel.org, robh@kernel.org, olteanv@gmail.com, linux-phy@lists.infradead.org, lee@kernel.org, mfd@lists.linux.dev, conor+dt@kernel.org, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, neil.armstrong@linaro.org, devicetree@vger.kernel.org In-Reply-To: <20260915-jh7110-clean-send-v4-18-f0e4fd6f2cc8@samsung.com> References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> <20260915-jh7110-clean-send-v4-18-f0e4fd6f2cc8@samsung.com> Date: Tue, 15 Sep 2026 15:46:16 +0000 Message-Id: <20260915154616.B1D171F000FF@smtp.kernel.org> X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg NCBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIGNsazogc3RhcmZpdmU6 IFVuc2FmZSBoYXJkd2FyZSBhY2Nlc3MgaW4gLnNldF9yYXRlIGNhdXNlcyBDUFUgc3RhbGwgZHVy aW5nIHByb2JlCi0gW01lZGl1bV0gY2xrOiBzdGFyZml2ZTogUHJlLVBMTCBpcyB1bmNvbmRpdGlv bmFsbHkgcG93ZXJlZCBvbiBpbiAuc2V0X3JhdGUgY2F1c2luZyBhIHBvd2VyIGxlYWsKLSBbTWVk aXVtXSBjbGs6IHN0YXJmaXZlOiBSZXNvdXJjZSBsaWZlY3ljbGUgaW52ZXJzaW9uIHdpdGggcmVm b2NsayBhbmQgZGV2cmVzIGNsb2NrIHByb3ZpZGVyCi0gW01lZGl1bV0gY2xrOiBzdGFyZml2ZTog RGF0YSByYWNlIG9uIGNhY2hlZCBjbG9jayBzdGF0ZSB2YXJpYWJsZXMgYmV0d2VlbiBDQ0YgYW5k IFBIWSBmcmFtZXdvcmtzCi0tCgpjb21taXQgNTQ2OWI3OTA5YWE5YmI4NjkwZWU5ZmJmZTE4ZWY1 N2Y0YzJkNTgyMApBdXRob3I6IE1pY2hhbCBXaWxjenluc2tpIDxtLndpbGN6eW5za2lAc2Ftc3Vu Zy5jb20+CgpwaHk6IHN0YXJmaXZlOiBBZGQgamg3MTEwLWlubm8taGRtaS1waHkgZHJpdmVyCgpB ZGQgdGhlIEhETUkgUEhZIGRyaXZlciBmb3IgdGhlIFN0YXJGaXZlIEpINzExMC4KCj4gZGlmZiAt LWdpdCBhL2RyaXZlcnMvcGh5L3N0YXJmaXZlL3BoeS1qaDcxMTAtaW5uby1oZG1pLmMgYi9kcml2 ZXJzL3BoeS9zdGFyZml2ZS9waHktamg3MTEwLWlubm8taGRtaS5jCj4gbmV3IGZpbGUgbW9kZSAx MDA2NDQKPiBpbmRleCAwMDAwMDAwMDAwMDAwLi4yNTc1Y2I1ZWQ2MjRhCj4gLS0tIC9kZXYvbnVs bAo+ICsrKyBiL2RyaXZlcnMvcGh5L3N0YXJmaXZlL3BoeS1qaDcxMTAtaW5uby1oZG1pLmMKPiBA QCAtMCwwICsxLDU3OSBAQAoKWyAuLi4gXQoKPiArc3RhdGljIGludCBzdGFyZml2ZV9oZG1pX3Bo eV9jbGtfc2V0X3JhdGUoc3RydWN0IGNsa19odyAqaHcsIHVuc2lnbmVkIGxvbmcgcmF0ZSwKPiAr CQkJCQkgIHVuc2lnbmVkIGxvbmcgcGFyZW50X3JhdGUpCj4gK3sKPiArCXN0cnVjdCBzdGFyZml2 ZV9oZG1pX3BoeSAqaW5ubyA9IHRvX3N0YXJmaXZlX2hkbWlfcGh5KGh3KTsKPiArCWNvbnN0IHN0 cnVjdCBpbm5vX2hkbWlfcGh5X3ByZV9wbGxfY29uZmlnICpjZmc7Cj4gKwo+ICsJLyoKPiArCSAq IFRoZSBKSDcxMTAgb25seSBkcml2ZXMgOGJwYywgc28gdGhlIFRNRFMgY2xvY2sgYWx3YXlzIG1h dGNoZXMgdGhlCj4gKwkgKiBwaXhlbCBjbG9jay4KPiArCSAqLwo+ICsJY2ZnID0gaW5ub19oZG1p X3BoeV9wcmVfcGxsX2xvb2t1cCgmaW5uby0+cHJlX3BsbCwgcmF0ZSwgcmF0ZSk7Cj4gKwlpZiAo SVNfRVJSKGNmZykpCj4gKwkJcmV0dXJuIFBUUl9FUlIoY2ZnKTsKPiArCj4gKwlkZXZfZGJnKGlu bm8tPmRldiwgIiVzIHJhdGUgJWx1IHRtZHNjbGsgJWx1XG4iLAo+ICsJCV9fZnVuY19fLCByYXRl LCBjZmctPnRtZHNjbG9jayk7Cj4gKwo+ICsJaWYgKGlubm8tPnBpeGNsb2NrID09IHJhdGUgJiYg aW5uby0+dG1kc2Nsb2NrID09IGNmZy0+dG1kc2Nsb2NrKQo+ICsJCXJldHVybiAwOwo+ICsKPiAr CWlubm9fdXBkYXRlX2JpdHMoaW5ubywgU1RGX0lOTk9fQklBU19DT05UUk9MLAo+ICsJCQkgU1RG X0lOTk9fQklBU19FTkFCTEUsIFNURl9JTk5PX0JJQVNfRU5BQkxFKTsKCltTZXZlcml0eTogSGln aF0KRG9lcyB0aGlzIGV4ZWN1dGUgYW4gdW5jbG9ja2VkIGhhcmR3YXJlIGFjY2VzcyBpZiB0aGUg Y2xvY2sgaXMgZ2F0ZWQ/CgpUaGUgY29tbWl0IG1lc3NhZ2Ugbm90ZXMgdGhhdCBhY2Nlc3Npbmcg dGhlIFBIWSByZWdpc3RlcnMgd2hpbGUgdGhlIEhETUkKY29udHJvbGxlcidzIHN5c3RlbSBjbG9j ayBpcyBnYXRlZCB3ZWRnZXMgdGhlIENQVS4gQmVjYXVzZQpzdGFyZml2ZV9oZG1pX3BoeV9wcm9i ZSgpIHVuY29uZGl0aW9uYWxseSBjYWxscyBjbGtfc2V0X3JhdGUoKSBiZWZvcmUgdGhlCnNpYmxp bmcgSERNSSBicmlkZ2UgZHJpdmVyIGhhcyBib3VuZCBhbmQgZW5hYmxlZCB0aGUgc2hhcmVkIHN5 c3RlbSBjbG9jaywgdGhlCmhhcmR3YXJlIGlzIGdhdGVkLgoKQ291bGQgYSBjbGtfaHdfaXNfcHJl cGFyZWQoaHcpIGNoZWNrIGJlIGFkZGVkIGhlcmUgc2ltaWxhcmx5IHRvIGhvdyBpdCB3YXMKdXNl ZCBpbiAucmVjYWxjX3JhdGU/Cgo+ICsJaW5ub193cml0ZShpbm5vLCBTVEZfSU5OT19SWF9DT05U Uk9MLCBTVEZfSU5OT19SWF9FTkFCTEUpOwo+ICsKPiArCWlubm9faGRtaV9waHlfcHJlX3BsbF9w b3dlcl9kb3duKCZpbm5vLT5wcmVfcGxsLCB0cnVlKTsKPiArCWlubm9faGRtaV9waHlfcHJlX3Bs bF9jb25maWd1cmUoJmlubm8tPnByZV9wbGwsIGNmZyk7Cj4gKwlpbm5vX2hkbWlfcGh5X3ByZV9w bGxfcG93ZXJfZG93bigmaW5uby0+cHJlX3BsbCwgZmFsc2UpOwoKW1NldmVyaXR5OiBNZWRpdW1d CldpbGwgdGhlIFByZS1QTEwgcmVtYWluIHBvd2VyZWQgb24gaW5kZWZpbml0ZWx5IGlmIHRoZSBj bG9jayBpc24ndCBwcmVwYXJlZD8KClNpbmNlIC5zZXRfcmF0ZSB0dXJucyB0aGUgUHJlLVBMTCBv biwgYW5kIHRoZSBkcml2ZXIgb21pdHMgdGhlIC5pc19wcmVwYXJlZApjYWxsYmFjayBpbiBzdGFy Zml2ZV9oZG1pX3BoeV9jbGtfb3BzLCB0aGUgQ0NGIHJlbGllcyBvbiB0aGUgc29mdHdhcmUgcHJl cGFyZQpjb3VudCAod2hpY2ggaXMgMCkuIFdoZW4gY2xrX2Rpc2FibGVfdW51c2VkKCkgcnVucywg aXQgc2tpcHMgdW5wcmVwYXJlZCBjbG9ja3MKd2l0aCBhIDAgY291bnQsIG1lYW5pbmcgLnVucHJl cGFyZSgpIHdvbid0IGJlIGludm9rZWQgdG8gdHVybiB0aGUgUExMIG9mZi4KCj4gKwo+ICsJaW5u by0+cGl4Y2xvY2sgPSByYXRlOwo+ICsJaW5uby0+dG1kc2Nsb2NrID0gY2ZnLT50bWRzY2xvY2s7 CgpbU2V2ZXJpdHk6IE1lZGl1bV0KQ291bGQgdGhlcmUgYmUgYSBkYXRhIHJhY2Ugb24gaW5uby0+ cGl4Y2xvY2sgYW5kIGlubm8tPnRtZHNjbG9jayBiZXR3ZWVuIHRoZQpDQ0YgYW5kIFBIWSBmcmFt ZXdvcmtzPwoKVGhlIENDRiBjYWxsYmFja3MgKHN1Y2ggYXMgLnNldF9yYXRlIGFuZCAucmVjYWxj X3JhdGUpIHJlYWQgYW5kIHdyaXRlCmlubm8tPnBpeGNsb2NrIGFuZCBpbm5vLT50bWRzY2xvY2sg dW5kZXIgdGhlIENDRiBjb3JlJ3MgcHJlcGFyZV9sb2NrLgpDb25jdXJyZW50bHksIHRoZSBQSFkg ZnJhbWV3b3JrIG9wZXJhdGlvbnMgKHN1Y2ggYXMgLnBvd2VyX29mZiBjYWxsaW5nCnN0YXJmaXZl X2hkbWlfcGh5X3Bvd2VyX2Rvd24oKSkgd3JpdGUgdG8gdGhlc2UgZXhhY3Qgc2FtZSB2YXJpYWJs ZXMgdW5kZXIgdGhlClBIWSBmcmFtZXdvcmsncyBpbnRlcm5hbCBwaHktPm11dGV4LgoKSWYgdXNl cnNwYWNlIHRyaWdnZXJzIGEgc3lzZnMgY2xvY2sgc3VtbWFyeSByZWFkICh0cmlnZ2VyaW5nIC5y ZWNhbGNfcmF0ZSkKY29uY3VycmVudGx5IHdpdGggYSBEUk0gZGlzcGxheSBtb2Rlc2V0IG9yIHBv d2VyIGRvd24gc2VxdWVuY2UsIGNvdWxkCi5yZWNhbGNfcmF0ZSBvdmVyd3JpdGUgdGhlIDAgc2V0 IGJ5IHBvd2VyX2Rvd24gd2l0aCBzdGFsZSBoYXJkd2FyZSB2YWx1ZXM/ClRoaXMgbWlnaHQgcHJl dmVudCBhIHN1YnNlcXVlbnQgc2V0X3JhdGUgZnJvbSBhcHBseWluZyB0aGUgY29ycmVjdCBzZXR0 aW5ncy4KCj4gKwo+ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qg Y2xrX29wcyBzdGFyZml2ZV9oZG1pX3BoeV9jbGtfb3BzID0gewo+ICsJLnByZXBhcmUgPSBzdGFy Zml2ZV9oZG1pX3BoeV9jbGtfcHJlcGFyZSwKPiArCS51bnByZXBhcmUgPSBzdGFyZml2ZV9oZG1p X3BoeV9jbGtfdW5wcmVwYXJlLAo+ICsJLnJlY2FsY19yYXRlID0gc3RhcmZpdmVfaGRtaV9waHlf Y2xrX3JlY2FsY19yYXRlLAo+ICsJLmRldGVybWluZV9yYXRlID0gc3RhcmZpdmVfaGRtaV9waHlf Y2xrX2RldGVybWluZV9yYXRlLAo+ICsJLnNldF9yYXRlID0gc3RhcmZpdmVfaGRtaV9waHlfY2xr X3NldF9yYXRlLAo+ICt9OwoKW1NldmVyaXR5OiBNZWRpdW1dClRoZSBvbWlzc2lvbiBvZiB0aGUg LmlzX3ByZXBhcmVkIGNhbGxiYWNrIGhlcmUgaXMgd2hhdCBjYXVzZXMKY2xrX2Rpc2FibGVfdW51 c2VkKCkgdG8gYXNzdW1lIHRoZSBjbG9jayBpcyBhbHJlYWR5IHBoeXNpY2FsbHkgZGlzYWJsZWQs CmxlYWRpbmcgdG8gdGhlIHBvd2VyIGxlYWsgbWVudGlvbmVkIGluIC5zZXRfcmF0ZS4KCj4gKwo+ ICtzdGF0aWMgdm9pZCBzdGFyZml2ZV9oZG1pX3BoeV9wb3dlcl9kb3duKHN0cnVjdCBzdGFyZml2 ZV9oZG1pX3BoeSAqaW5ubykKPiArewo+ICsJaW5ub193cml0ZShpbm5vLCBTVEZfSU5OT19UTURT X0NPTlRST0wsIDB4MDApOwo+ICsJaW5ub193cml0ZShpbm5vLCBTVEZfSU5OT19TRVJJQUxJRVJf Q09OVFJPTCwgMHgwMCk7Cj4gKwlpbm5vX3dyaXRlKGlubm8sIFNURl9JTk5PX0xET19DT05UUk9M LCAweDAwKTsKPiArCWlubm9fdXBkYXRlX2JpdHMoaW5ubywgU1RGX0lOTk9fQklBU19DT05UUk9M LAo+ICsJCQkgU1RGX0lOTk9fQklBU19FTkFCTEUsIDB4MDApOwo+ICsJaW5ub193cml0ZShpbm5v LCBTVEZfSU5OT19SWF9DT05UUk9MLCAweDAwKTsKPiArCj4gKwkvKiBQb3dlciBkb3duIFBvc3Qt UExMICovCj4gKwlpbm5vX3VwZGF0ZV9iaXRzKGlubm8sIFNURl9JTk5PX1BPU1RfUExMX0RJVl8x LAo+ICsJCQkgU1RGX0lOTk9fUE9TVF9QTExfUE9XRVJfRE9XTiwKPiArCQkJIFNURl9JTk5PX1BP U1RfUExMX1BPV0VSX0RPV04pOwo+ICsKPiArCWlubm8tPnRtZHNjbG9jayA9IDA7Cj4gKwlpbm5v LT5waXhjbG9jayA9IDA7CgpbU2V2ZXJpdHk6IE1lZGl1bV0KVGhpcyBpcyB3aGVyZSB0aGUgY29u Y3VycmVudCB3cml0ZXMgZnJvbSB0aGUgUEhZIGZyYW1ld29yayBoYXBwZW4sIGFzIG5vdGVkCmlu IHRoZSBwcmV2aW91cyBjb21tZW50IGFib3V0IHRoZSBkYXRhIHJhY2Ugd2l0aCB0aGUgQ0NGIGNh bGxiYWNrcy4KCj4gK30KClsgLi4uIF0KCj4gK3N0YXRpYyBpbnQgc3RhcmZpdmVfaGRtaV9waHlf cHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiArewoKWyAuLi4gXQoKPiArCXJl dCA9IG9mX2Nsa19hZGRfcHJvdmlkZXIoZGV2LT5vZl9ub2RlLCBvZl9jbGtfc3JjX3NpbXBsZV9n ZXQsIGlubm8tPnBoeWNsayk7Cj4gKwlpZiAocmV0KSB7Cj4gKwkJZGV2X2VycihkZXYsICJGYWls ZWQgdG8gYWRkIGNsb2NrIHByb3ZpZGVyOiAlZFxuIiwgcmV0KTsKPiArCQlnb3RvIGVycl9kaXNh YmxlX3JlZm9jbGs7Cj4gKwl9Cj4gKwo+ICsJcmV0ID0gY2xrX3NldF9yYXRlKGlubm8tPnBoeWNs aywgMjk3MDAwMDAwKTsKCltTZXZlcml0eTogSGlnaF0KVGhpcyB1bmNvbmRpdGlvbmFsbHkgdHJp Z2dlcnMgYSByYXRlIGNoYW5nZSBkdXJpbmcgcHJvYmUsIHdoaWNoIGxlYWRzIHRvIHRoZQp1bnNh ZmUgaGFyZHdhcmUgYWNjZXNzIGluIC5zZXRfcmF0ZSBkZXNjcmliZWQgZWFybGllciwgc2luY2Ug dGhlIHNpYmxpbmcgYnJpZGdlCmRyaXZlciBpcyBub3QgZ3VhcmFudGVlZCB0byBoYXZlIGVuYWJs ZWQgdGhlIHNoYXJlZCBzeXN0ZW0gY2xvY2sgeWV0LgoKPiArCWlmIChyZXQpIHsKPiArCQlkZXZf ZXJyKGRldiwgIkZhaWxlZCB0byBzZXQgZGVmYXVsdCByYXRlOiAlZFxuIiwgcmV0KTsKPiArCQln b3RvIGVycl9kZWxfY2xrX3Byb3ZpZGVyOwo+ICsJfQo+ICsKPiArCS8qIENyZWF0ZSBhbmQgcmVn aXN0ZXIgdGhlIFBIWSBwcm92aWRlciAqLwo+ICsJaW5uby0+cGh5ID0gZGV2bV9waHlfY3JlYXRl KGlubm8tPmRldiwgTlVMTCwgJnN0YXJmaXZlX2hkbWlfcGh5X29wcyk7Cj4gKwlpZiAoSVNfRVJS KGlubm8tPnBoeSkpIHsKPiArCQlyZXQgPSBQVFJfRVJSKGlubm8tPnBoeSk7Cj4gKwkJZGV2X2Vy cihpbm5vLT5kZXYsICJmYWlsZWQgdG8gY3JlYXRlIEhETUkgUEhZOiAlZFxuIiwgcmV0KTsKPiAr CQlnb3RvIGVycl9kZWxfY2xrX3Byb3ZpZGVyOwo+ICsJfQo+ICsKPiArCXBoeV9zZXRfZHJ2ZGF0 YShpbm5vLT5waHksIGlubm8pOwo+ICsKPiArCXBoeV9wcm92aWRlciA9IGRldm1fb2ZfcGh5X3By b3ZpZGVyX3JlZ2lzdGVyKGlubm8tPmRldiwKPiArCQkJCQkJICAgICBvZl9waHlfc2ltcGxlX3hs YXRlKTsKPiArCXJldCA9IFBUUl9FUlJfT1JfWkVSTyhwaHlfcHJvdmlkZXIpOwo+ICsJaWYgKHJl dCkKPiArCQlnb3RvIGVycl9kZWxfY2xrX3Byb3ZpZGVyOwo+ICsKPiArCXJldHVybiAwOwo+ICsK PiArZXJyX2RlbF9jbGtfcHJvdmlkZXI6Cj4gKwlvZl9jbGtfZGVsX3Byb3ZpZGVyKGRldi0+b2Zf bm9kZSk7Cj4gK2Vycl9kaXNhYmxlX3JlZm9jbGs6Cj4gKwljbGtfZGlzYWJsZV91bnByZXBhcmUo aW5uby0+cmVmb2Nsayk7Cj4gKwlyZXR1cm4gcmV0OwoKW1NldmVyaXR5OiBNZWRpdW1dCklzIGl0 IHNhZmUgdG8gbWFudWFsbHkgZGlzYWJsZSB0aGUgcmVmZXJlbmNlIGNsb2NrIGhlcmUgYmVmb3Jl IGRldnJlcwp1bnJlZ2lzdGVycyB0aGUgY2xvY2sgYW5kIFBIWSBwcm92aWRlcnM/CgpUaGUgY2xv Y2sgYW5kIFBIWSBwcm92aWRlcnMgYXJlIHJlZ2lzdGVyZWQgdXNpbmcgZGV2bV9jbGtfcmVnaXN0 ZXIoKSBhbmQKZGV2bV9vZl9waHlfcHJvdmlkZXJfcmVnaXN0ZXIoKS4gRGlzYWJsaW5nIHJlZm9j bGsgbWFudWFsbHkgaGVyZSAoYW5kIGluCnJlbW92ZSkgY3JlYXRlcyBhIHdpbmRvdyB3aGVyZSBv cGVyYXRpb25zIGNvdWxkIGV4ZWN1dGUgd2l0aCBhIGRpc2FibGVkIHBhcmVudApjbG9jayBpZiBh IGNvbnN1bWVyIHRyaWdnZXJzIGEgY2xvY2sgb3IgUEhZIG9wZXJhdGlvbiBiZWZvcmUgZGV2cmVz IGNsZWFucyB1cAp0aGUgcHJvdmlkZXJzLgoKV291bGQgaXQgYmUgYmV0dGVyIHRvIGJpbmQgdGhl IHJlZm9jbGsgZW5hYmxlIHN0YXRlIHRvIGRldnJlcyB2aWEKZGV2bV9jbGtfZ2V0X2VuYWJsZWQo KSBvciBkZXZtX2FkZF9hY3Rpb25fb3JfcmVzZXQoKT8KCj4gK30KPiArCj4gK3N0YXRpYyB2b2lk IHN0YXJmaXZlX2hkbWlfcGh5X3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQo+ ICt7Cj4gKwlzdHJ1Y3Qgc3RhcmZpdmVfaGRtaV9waHkgKmlubm8gPSBwbGF0Zm9ybV9nZXRfZHJ2 ZGF0YShwZGV2KTsKPiArCj4gKwlvZl9jbGtfZGVsX3Byb3ZpZGVyKHBkZXYtPmRldi5vZl9ub2Rl KTsKPiArCWNsa19kaXNhYmxlX3VucHJlcGFyZShpbm5vLT5yZWZvY2xrKTsKCltTZXZlcml0eTog TWVkaXVtXQpBcyBpbiB0aGUgcHJvYmUgZXJyb3IgcGF0aCwgbWFudWFsbHkgZGlzYWJsaW5nIHRo ZSByZWZlcmVuY2UgY2xvY2sgYmVmb3JlCmRldnJlcyB1bnJlZ2lzdGVycyB0aGUgcHJvdmlkZXJz IGNyZWF0ZXMgYSB1c2UtYWZ0ZXItZGlzYWJsZSB3aW5kb3cuCgo+ICt9CgotLSAKU2FzaGlrbyBB SSByZXZpZXcgwrcgaHR0cHM6Ly9zYXNoaWtvLmRldi8jL3BhdGNoc2V0LzIwMjYwOTE1LWpoNzEx MC1jbGVhbi1zZW5kLXY0LTAtZjBlNGZkNmYyY2M4QHNhbXN1bmcuY29tP3BhcnQ9MTgKCi0tIAps aW51eC1waHkgbWFpbGluZyBsaXN0CmxpbnV4LXBoeUBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHBz Oi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LXBoeQo= From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D6563BB67B; Tue, 15 Sep 2026 15:46:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789487179; cv=none; b=Z6va+kzRr1/wKZbOXVGOIY2we8T6Wwa51YSckbyrrbcEDsOvv1FvWywHmjwNlD5HgLRZ8c09oeV1b1DKh31U3nleio3rPMWDE6i6OA22lnZICznTCJaTfb2sZtHlAr1naTDVdeUgVosI4q6qX3jdVYPguzCT35gEuQV6Sr/sYeA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789487179; c=relaxed/simple; bh=p1PDvb51V6PvN5ZA9PH/4AzJgaVNCIMS73kM19scPDs=; h=From:Subject:To:Cc:In-Reply-To:References:Content-Type:Date: Message-Id; b=ex/AEcWxWYbMZ8XkCBrEHsA3hv+zGNRC3Drw1jR4fpTmk7donEQkj6oDbCri80Rw7ixL7VDROvtlP+M1U+YX+8lgF0p2E0AOWB0kKYNtihM75HLvKV5sJGJyDD/AQP7rgZNX18U/r0JoFlOnpUapotK0p9srndNmLLezJa9uzhU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Vi7apQxc; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Vi7apQxc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1D171F000FF; Tue, 15 Sep 2026 15:46:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1789487177; bh=mjVSAPDqPKP4DItjJf1WRLNRKD0I+SD0o8c0mchPH3U=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=Vi7apQxczYynDIBLO65dXI6QHAkCcrqLXH7OW3PXQzj8b4GDy1gviRnGjulpMMVVn AZ/9GNPdOqaM2D1vtzBdQbmYT29IYJwGKXADhSbIctOOK965blDkGfZ4RS4GQ7h2nL FB06xbZC/q2U2zsS7irF4MgdsSTw/+1pfPBjVI3fxFTWCPo8eRnMeOSjkDcHpcoX3n zb/4U5V1bcEK6yM4NpezS9bCd5pPyVzCJKXfR/sKo6CGCT9b2zvyQBzg8dmzLKPL4N cHwuEg5FDmZqYwFcQfkj153q2TE/rhTDkp7T1/l2qXOUizc1gAFPA+Zlutrtjhn78e lIkvx1zC3teKg== From: sashiko-bot@kernel.org Subject: Re: [PATCH v4 18/20] phy: starfive: Add jh7110-inno-hdmi-phy driver Reply-To: sashiko-reviews@lists.linux.dev To: "Michal Wilczynski" Cc: vkoul@kernel.org, robh@kernel.org, olteanv@gmail.com, linux-phy@lists.infradead.org, lee@kernel.org, mfd@lists.linux.dev, conor+dt@kernel.org, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, neil.armstrong@linaro.org, devicetree@vger.kernel.org In-Reply-To: <20260915-jh7110-clean-send-v4-18-f0e4fd6f2cc8@samsung.com> References: <20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com> <20260915-jh7110-clean-send-v4-18-f0e4fd6f2cc8@samsung.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Tue, 15 Sep 2026 15:46:16 +0000 Message-Id: <20260915154616.B1D171F000FF@smtp.kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Thank you for your contribution! Sashiko AI review found 4 potential issue(= s) to consider: - [High] clk: starfive: Unsafe hardware access in .set_rate causes CPU stal= l during probe - [Medium] clk: starfive: Pre-PLL is unconditionally powered on in .set_rat= e causing a power leak - [Medium] clk: starfive: Resource lifecycle inversion with refoclk and dev= res clock provider - [Medium] clk: starfive: Data race on cached clock state variables between= CCF and PHY frameworks -- commit 5469b7909aa9bb8690ee9fbfe18ef57f4c2d5820 Author: Michal Wilczynski phy: starfive: Add jh7110-inno-hdmi-phy driver Add the HDMI PHY driver for the StarFive JH7110. > diff --git a/drivers/phy/starfive/phy-jh7110-inno-hdmi.c b/drivers/phy/st= arfive/phy-jh7110-inno-hdmi.c > new file mode 100644 > index 0000000000000..2575cb5ed624a > --- /dev/null > +++ b/drivers/phy/starfive/phy-jh7110-inno-hdmi.c > @@ -0,0 +1,579 @@ [ ... ] > +static int starfive_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned lo= ng rate, > + unsigned long parent_rate) > +{ > + struct starfive_hdmi_phy *inno =3D to_starfive_hdmi_phy(hw); > + const struct inno_hdmi_phy_pre_pll_config *cfg; > + > + /* > + * The JH7110 only drives 8bpc, so the TMDS clock always matches the > + * pixel clock. > + */ > + cfg =3D inno_hdmi_phy_pre_pll_lookup(&inno->pre_pll, rate, rate); > + if (IS_ERR(cfg)) > + return PTR_ERR(cfg); > + > + dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", > + __func__, rate, cfg->tmdsclock); > + > + if (inno->pixclock =3D=3D rate && inno->tmdsclock =3D=3D cfg->tmdsclock) > + return 0; > + > + inno_update_bits(inno, STF_INNO_BIAS_CONTROL, > + STF_INNO_BIAS_ENABLE, STF_INNO_BIAS_ENABLE); [Severity: High] Does this execute an unclocked hardware access if the clock is gated? The commit message notes that accessing the PHY registers while the HDMI controller's system clock is gated wedges the CPU. Because starfive_hdmi_phy_probe() unconditionally calls clk_set_rate() before the sibling HDMI bridge driver has bound and enabled the shared system clock, t= he hardware is gated. Could a clk_hw_is_prepared(hw) check be added here similarly to how it was used in .recalc_rate? > + inno_write(inno, STF_INNO_RX_CONTROL, STF_INNO_RX_ENABLE); > + > + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, true); > + inno_hdmi_phy_pre_pll_configure(&inno->pre_pll, cfg); > + inno_hdmi_phy_pre_pll_power_down(&inno->pre_pll, false); [Severity: Medium] Will the Pre-PLL remain powered on indefinitely if the clock isn't prepared? Since .set_rate turns the Pre-PLL on, and the driver omits the .is_prepared callback in starfive_hdmi_phy_clk_ops, the CCF relies on the software prepa= re count (which is 0). When clk_disable_unused() runs, it skips unprepared clo= cks with a 0 count, meaning .unprepare() won't be invoked to turn the PLL off. > + > + inno->pixclock =3D rate; > + inno->tmdsclock =3D cfg->tmdsclock; [Severity: Medium] Could there be a data race on inno->pixclock and inno->tmdsclock between the CCF and PHY frameworks? The CCF callbacks (such as .set_rate and .recalc_rate) read and write inno->pixclock and inno->tmdsclock under the CCF core's prepare_lock. Concurrently, the PHY framework operations (such as .power_off calling starfive_hdmi_phy_power_down()) write to these exact same variables under t= he PHY framework's internal phy->mutex. If userspace triggers a sysfs clock summary read (triggering .recalc_rate) concurrently with a DRM display modeset or power down sequence, could .recalc_rate overwrite the 0 set by power_down with stale hardware values? This might prevent a subsequent set_rate from applying the correct settings. > + > + return 0; > +} > + > +static const struct clk_ops starfive_hdmi_phy_clk_ops =3D { > + .prepare =3D starfive_hdmi_phy_clk_prepare, > + .unprepare =3D starfive_hdmi_phy_clk_unprepare, > + .recalc_rate =3D starfive_hdmi_phy_clk_recalc_rate, > + .determine_rate =3D starfive_hdmi_phy_clk_determine_rate, > + .set_rate =3D starfive_hdmi_phy_clk_set_rate, > +}; [Severity: Medium] The omission of the .is_prepared callback here is what causes clk_disable_unused() to assume the clock is already physically disabled, leading to the power leak mentioned in .set_rate. > + > +static void starfive_hdmi_phy_power_down(struct starfive_hdmi_phy *inno) > +{ > + inno_write(inno, STF_INNO_TMDS_CONTROL, 0x00); > + inno_write(inno, STF_INNO_SERIALIER_CONTROL, 0x00); > + inno_write(inno, STF_INNO_LDO_CONTROL, 0x00); > + inno_update_bits(inno, STF_INNO_BIAS_CONTROL, > + STF_INNO_BIAS_ENABLE, 0x00); > + inno_write(inno, STF_INNO_RX_CONTROL, 0x00); > + > + /* Power down Post-PLL */ > + inno_update_bits(inno, STF_INNO_POST_PLL_DIV_1, > + STF_INNO_POST_PLL_POWER_DOWN, > + STF_INNO_POST_PLL_POWER_DOWN); > + > + inno->tmdsclock =3D 0; > + inno->pixclock =3D 0; [Severity: Medium] This is where the concurrent writes from the PHY framework happen, as noted in the previous comment about the data race with the CCF callbacks. > +} [ ... ] > +static int starfive_hdmi_phy_probe(struct platform_device *pdev) > +{ [ ... ] > + ret =3D of_clk_add_provider(dev->of_node, of_clk_src_simple_get, inno->= phyclk); > + if (ret) { > + dev_err(dev, "Failed to add clock provider: %d\n", ret); > + goto err_disable_refoclk; > + } > + > + ret =3D clk_set_rate(inno->phyclk, 297000000); [Severity: High] This unconditionally triggers a rate change during probe, which leads to the unsafe hardware access in .set_rate described earlier, since the sibling br= idge driver is not guaranteed to have enabled the shared system clock yet. > + if (ret) { > + dev_err(dev, "Failed to set default rate: %d\n", ret); > + goto err_del_clk_provider; > + } > + > + /* Create and register the PHY provider */ > + inno->phy =3D devm_phy_create(inno->dev, NULL, &starfive_hdmi_phy_ops); > + if (IS_ERR(inno->phy)) { > + ret =3D PTR_ERR(inno->phy); > + dev_err(inno->dev, "failed to create HDMI PHY: %d\n", ret); > + goto err_del_clk_provider; > + } > + > + phy_set_drvdata(inno->phy, inno); > + > + phy_provider =3D devm_of_phy_provider_register(inno->dev, > + of_phy_simple_xlate); > + ret =3D PTR_ERR_OR_ZERO(phy_provider); > + if (ret) > + goto err_del_clk_provider; > + > + return 0; > + > +err_del_clk_provider: > + of_clk_del_provider(dev->of_node); > +err_disable_refoclk: > + clk_disable_unprepare(inno->refoclk); > + return ret; [Severity: Medium] Is it safe to manually disable the reference clock here before devres unregisters the clock and PHY providers? The clock and PHY providers are registered using devm_clk_register() and devm_of_phy_provider_register(). Disabling refoclk manually here (and in remove) creates a window where operations could execute with a disabled par= ent clock if a consumer triggers a clock or PHY operation before devres cleans = up the providers. Would it be better to bind the refoclk enable state to devres via devm_clk_get_enabled() or devm_add_action_or_reset()? > +} > + > +static void starfive_hdmi_phy_remove(struct platform_device *pdev) > +{ > + struct starfive_hdmi_phy *inno =3D platform_get_drvdata(pdev); > + > + of_clk_del_provider(pdev->dev.of_node); > + clk_disable_unprepare(inno->refoclk); [Severity: Medium] As in the probe error path, manually disabling the reference clock before devres unregisters the providers creates a use-after-disable window. > +} --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260915-jh7110-cle= an-send-v4-0-f0e4fd6f2cc8@samsung.com?part=3D18