Re: [PATCH v6 5/6] tests/qtest: Add RISC-V ACPI bios tables test for CXL

[Jonathan Cameron <jic23@kernel.org>]

On Mon,  7 Sep 2026 17:37:32 +0800
Chen Pei <cp0613@linux.alibaba.com> wrote:

> Add test_acpi_riscv64_virt_tcg_cxl() to verify that enabling CXL on
> the RISC-V virt machine produces correct ACPI tables, including the
> ACPI0017 CXLM device with _DEP in the DSDT and the CEDT table.
> 
> The test boots with cxl=on, one pxb-cxl bus (bus_nr=12), a CXL root
> port, a cxl-type3 device and a fixed memory window, mirroring the
> existing x86 q35 CXL test pattern.
> 
> Since pxb-cxl is a root bus, using -cdrom causes QEMU to auto-plug the
> cdrom drive into pxb-cxl, triggering "Only PCI/PCIe bridges can be
> plugged into pxb-cxl".  The ISO is instead attached explicitly via a
> virtio-scsi-pci controller on pcie.0, following the same approach as
> test_acpi_aarch64_virt_tcg_pxb().
> 
> Acked-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Junjie Cao <junjie.cao@intel.com>
> Tested-by: Junjie Cao <junjie.cao@intel.com>
> Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>

One possible extra thing below and a general comment. This does the job
though so no need to change anything.

Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>


> ---
>  tests/qtest/bios-tables-test.c | 54 ++++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index f6dfa4131b..41c0d6a295 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -2214,6 +2214,56 @@ static void test_acpi_riscv64_virt_tcg(void)
>      free_test_data(&data);
>  }
>  
> +#ifdef CONFIG_POSIX
> +static void test_acpi_riscv64_virt_tcg_cxl(void)
> +{
> +    gchar *tmp_path = g_dir_make_tmp("qemu-test-cxl.XXXXXX", NULL);
> +    gchar *params;
> +
> +    test_data data = {
> +        .machine = "virt",
> +        .arch = "riscv64",
> +        .tcg_only = true,
> +        .uefi_fl1 = "pc-bios/edk2-riscv64-code.fd",
> +        .uefi_fl2 = "pc-bios/edk2-riscv64-vars.fd",
> +        .ram_start = 0x80000000ULL,
> +        .scan_len = 128ULL * MiB,
> +        .variant = ".cxl",
> +    };
> +
> +    /*
> +     * While using -cdrom, the cdrom would auto-plug into pxb-cxl because
> +     * its bus is also a root bus, triggering "Only PCI/PCIe bridges can be
> +     * plugged into pxb-cxl".  Attach the ISO explicitly to a scsi controller
> +     * on pcie.0 instead, following the same pattern as
> +     * test_acpi_aarch64_virt_tcg_pxb().
> +     */
> +    params = g_strdup_printf("-cpu rva22s64"
> +                             " -machine cxl=on"
> +                             " -device pcie-root-port,chassis=1,id=pci.1,bus=pcie.0"
> +                             " -device virtio-scsi-pci,id=scsi0,bus=pci.1"
> +                             " -drive file=tests/data/uefi-boot-images/"
> +                             "bios-tables-test.riscv64.iso.qcow2,"
> +                             "if=none,media=cdrom,id=drive-scsi0-0-0-1,readonly=on"
> +                             " -device scsi-cd,bus=scsi0.0,scsi-id=0,"
> +                             "drive=drive-scsi0-0-0-1,id=scsi0-0-0-1,bootindex=1"
> +                             " -object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M"
> +                             " -object memory-backend-file,id=lsa1,mem-path=%s,size=256M"
> +                             " -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1"
> +                             " -device cxl-rp,port=0,bus=cxl.1,id=rp1,chassis=0,slot=2"
> +                             " -device cxl-type3,bus=rp1,persistent-memdev=cxl-mem1,lsa=lsa1"

Only thing maybe to consider adding is the serial number given the problems we've had with
that in the past and that persistent mem is basically unuseable without one (it ends
up as part of the stuff stored in LSA).

I am a bit curious if you actually care enough about persistent for that to be better to
test than volatile, but doesn't really matter wrt to what is being tested in practice
which is the arch integration.

> +                             " -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,"
> +                             "cxl-fmw.0.interleave-granularity=8k",
> +                             tmp_path, tmp_path);
> +    test_acpi_one(params, &data);
> +
> +    g_free(params);
> +    g_assert(g_rmdir(tmp_path) == 0);
> +    g_free(tmp_path);
> +    free_test_data(&data);
> +}
> +#endif /* CONFIG_POSIX */
> +
>  static void test_acpi_aarch64_virt_tcg(void)
>  {
>      test_data data = {
> @@ -2971,6 +3021,10 @@ int main(int argc, char *argv[])
>                             test_acpi_riscv64_virt_tcg_numamem);
>              qtest_add_func("acpi/virt/acpispcr",
>                             test_acpi_riscv64_virt_tcg_acpi_spcr);
> +#ifdef CONFIG_POSIX
> +            qtest_add_func("acpi/virt/cxl",
> +                           test_acpi_riscv64_virt_tcg_cxl);
> +#endif
>          }
>      } else if (strcmp(arch, "loongarch64") == 0) {
>          if (has_tcg && qtest_has_machine("virt")) {