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Tue, 15 Sep 2026 21:16:38 -0700 (PDT) From: Reza Kurniawan Date: Wed, 16 Sep 2026 04:16:03 +0000 Subject: [PATCH v3 2/3] clk: qcom: Add Global Clock Controller (GCC) driver for MSM8917 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260916-msm8917-support-v3-2-35103cb4e01e@gmail.com> References: <20260916-msm8917-support-v3-0-35103cb4e01e@gmail.com> In-Reply-To: <20260916-msm8917-support-v3-0-35103cb4e01e@gmail.com> To: u-boot-qcom@groups.io, u-boot@lists.u-boot-project.org Cc: Sumit Garg , Tom Rini , Ilias Apalodimas , Casey Connolly , Neil Armstrong , Balaji Selvanathan , Lukasz Majewski , Alexey Minnekhanov , Luca Weiss , Reza Kurniawan X-Mailer: b4 0.15.2 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Add Global Clock Controller (GCC) driver for MSM8917 to manage clocks, resets, and gdscs. This driver includes the essential clocks and resets for U-Boot to function. Taken from Linux commit 08df884 ("Merge tag 'thermal-7.3-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm") at drivers/clk/qcom/gcc-msm8917.c Signed-off-by: Reza Kurniawan --- configs/qcom_defconfig | 1 + drivers/clk/qcom/Kconfig | 8 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-msm8917.c | 210 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 220 insertions(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 7d4a2b589..59cad58a9 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -57,6 +57,7 @@ CONFIG_CLK_STUB=y CONFIG_CLK_QCOM_APQ8016=y CONFIG_CLK_QCOM_APQ8096=y CONFIG_CLK_QCOM_MILOS=y +CONFIG_CLK_QCOM_MSM8917=y CONFIG_CLK_QCOM_QCM2290=y CONFIG_CLK_QCOM_QCS404=y CONFIG_CLK_QCOM_QCS615=y diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 95b650831..d8469ad5f 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -55,6 +55,14 @@ config CLK_QCOM_MILOS on the Snapdragon Milos SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_MSM8917 + bool "Qualcomm MSM8917 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon MSM8917 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_QCM2290 bool "Qualcomm QCM2290 GCC" select CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 1adca029b..6478ec322 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o obj-$(CONFIG_CLK_QCOM_IPQ5424) += clock-ipq5424.o obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o obj-$(CONFIG_CLK_QCOM_MILOS) += clock-milos.o +obj-$(CONFIG_CLK_QCOM_MSM8917) += clock-msm8917.o obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o obj-$(CONFIG_CLK_QCOM_QCS8300) += clock-qcs8300.o diff --git a/drivers/clk/qcom/clock-msm8917.c b/drivers/clk/qcom/clock-msm8917.c new file mode 100644 index 000000000..11ee0a7c0 --- /dev/null +++ b/drivers/clk/qcom/clock-msm8917.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Clock drivers for Qualcomm MSM8917 + * + * (C) Copyright 2026 Reza Kurniawan + * + */ + +#include +#include +#include +#include + +#include "clock-qcom.h" + +#define CFG_CLK_SRC_GPLL4_SDCC1 (2 << 8) + +/* USB clock control register */ +#define USB_HS_SYSTEM_CMD_RCGR (0x41010) + +/* SDCC clock control registers */ +#define SDCC1_APPS_CMD_RCGR (0x42004) +#define SDCC2_APPS_CMD_RCGR (0x43004) + +/* UART clock control registers */ +#define BLSP1_UART1_APPS_CMD_RCGR (0x02044) +#define BLSP1_UART2_APPS_CMD_RCGR (0x03034) +#define BLSP2_UART1_APPS_CMD_RCGR (0x0c044) +#define BLSP2_UART2_APPS_CMD_RCGR (0x0d034) + +static const struct gate_clk msm8917_clks[] = { + GATE_CLK_POLLED(GCC_BLSP1_UART1_APPS_CLK, 0x0203c, BIT(0), 0x0203c), + GATE_CLK_POLLED(GCC_BLSP1_UART2_APPS_CLK, 0x0302c, BIT(0), 0x0302c), + GATE_CLK_POLLED(GCC_BLSP2_UART1_APPS_CLK, 0x0c03c, BIT(0), 0x0c03c), + GATE_CLK_POLLED(GCC_BLSP2_UART2_APPS_CLK, 0x0d02c, BIT(0), 0x0d02c), + GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x4201c, BIT(0), 0x4201c), + GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x42018, BIT(0), 0x42018), + GATE_CLK_POLLED(GCC_SDCC2_AHB_CLK, 0x4301c, BIT(0), 0x4301c), + GATE_CLK_POLLED(GCC_SDCC2_APPS_CLK, 0x43018, BIT(0), 0x43018), + GATE_CLK_POLLED(GCC_USB_HS_PHY_CFG_AHB_CLK, 0x41030, BIT(0), 0x41030), + GATE_CLK_POLLED(GCC_USB_HS_AHB_CLK, 0x41008, BIT(0), 0x41008), + GATE_CLK_POLLED(GCC_USB_HS_SYSTEM_CLK, 0x41004, BIT(0), 0x41004), + GATE_CLK_POLLED(GCC_USB2A_PHY_SLEEP_CLK, 0x4102c, BIT(0), 0x4102c) +}; + +static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = { + F(3686400, CFG_CLK_SRC_GPLL0, 1, 72, 15625), + F(7372800, CFG_CLK_SRC_GPLL0, 1, 144, 15625), + F(14745600, CFG_CLK_SRC_GPLL0, 1, 288, 15625), + F(16000000, CFG_CLK_SRC_GPLL0, 10, 1, 5), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(24000000, CFG_CLK_SRC_GPLL0, 1, 3, 100), + F(25000000, CFG_CLK_SRC_GPLL0, 16, 1, 2), + F(32000000, CFG_CLK_SRC_GPLL0, 1, 1, 25), + F(40000000, CFG_CLK_SRC_GPLL0, 1, 1, 20), + F(46400000, CFG_CLK_SRC_GPLL0, 1, 29, 500), + F(48000000, CFG_CLK_SRC_GPLL0, 1, 3, 50), + F(51200000, CFG_CLK_SRC_GPLL0, 1, 8, 125), + F(56000000, CFG_CLK_SRC_GPLL0, 1, 7, 100), + F(58982400, CFG_CLK_SRC_GPLL0, 1, 1152, 15625), + F(60000000, CFG_CLK_SRC_GPLL0, 1, 3, 40), + F(64000000, CFG_CLK_SRC_GPLL0, 1, 2, 25), + { } +}; + +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { + F(144000, CFG_CLK_SRC_CXO, 16, 3, 25), + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(20000000, CFG_CLK_SRC_GPLL0, 10, 1, 4), + F(25000000, CFG_CLK_SRC_GPLL0, 16, 1, 2), + F(50000000, CFG_CLK_SRC_GPLL0, 16, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0, 8, 0, 0), + F(177770000, CFG_CLK_SRC_GPLL0, 4.5, 0, 0), + F(192000000, CFG_CLK_SRC_GPLL4_SDCC1, 6, 0, 0), + F(200000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + F(384000000, CFG_CLK_SRC_GPLL4_SDCC1, 3, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { + F(144000, CFG_CLK_SRC_CXO, 16, 3, 25), + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(20000000, CFG_CLK_SRC_GPLL0, 10, 1, 4), + F(25000000, CFG_CLK_SRC_GPLL0, 16, 1, 2), + F(50000000, CFG_CLK_SRC_GPLL0, 16, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0, 8, 0, 0), + F(177770000, CFG_CLK_SRC_GPLL0, 4.5, 0, 0), + F(200000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = { + F(80000000, CFG_CLK_SRC_GPLL0, 10, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0, 8, 0, 0), + F(133330000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + F(177780000, CFG_CLK_SRC_GPLL0, 4.5, 0, 0), + { } +}; + +static int msm8917_enable(struct clk *clk) +{ + struct msm_clk_priv *priv; + + priv = dev_get_priv(clk->dev); + return qcom_gate_clk_en(priv, clk->id); +} + +static ulong msm8917_uart_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + u32 cmd_rcgr; + + switch (clk->id) { + case GCC_BLSP1_UART1_APPS_CLK: + cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR; + break; + case GCC_BLSP1_UART2_APPS_CLK: + cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR; + break; + case GCC_BLSP2_UART1_APPS_CLK: + cmd_rcgr = BLSP2_UART1_APPS_CMD_RCGR; + break; + case GCC_BLSP2_UART2_APPS_CLK: + cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR; + break; + default: + return 0; + } + + freq = qcom_find_freq(ftbl_blsp_uart_apps_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, cmd_rcgr, + freq->pre_div, freq->m, freq->n, freq->src, 16); + + return freq->freq; +} + +static ulong msm8917_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + + switch (clk->id) { + case GCC_BLSP1_UART1_APPS_CLK: + case GCC_BLSP1_UART2_APPS_CLK: + case GCC_BLSP2_UART1_APPS_CLK: + case GCC_BLSP2_UART2_APPS_CLK: + return msm8917_uart_set_rate(clk, rate); + case GCC_SDCC1_APPS_CLK: + freq = qcom_find_freq(ftbl_sdcc1_apps_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, SDCC1_APPS_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_SDCC2_APPS_CLK: + freq = qcom_find_freq(ftbl_sdcc2_apps_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB_HS_SYSTEM_CLK: + freq = qcom_find_freq(ftbl_usb_hs_system_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, USB_HS_SYSTEM_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 0); + return freq->freq; + default: + break; + } + + return 0; +} + +static const struct qcom_reset_map msm8917_resets[] = { + [GCC_CAMSS_MICRO_BCR] = { 0x56008 }, + [GCC_MSS_BCR] = { 0x71000 }, + [GCC_QUSB2_PHY_BCR] = { 0x4103c }, + [GCC_USB_HS_BCR] = { 0x41000 }, + [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 }, + [GCC_MDSS_BCR] = { 0x4d074 }, +}; + +static const struct qcom_power_map msm8917_gdscs[] = { + [MDSS_GDSC] = { 0x4d078 }, +}; + +static struct msm_clk_data msm8917_gcc_data = { + .resets = msm8917_resets, + .num_resets = ARRAY_SIZE(msm8917_resets), + .clks = msm8917_clks, + .num_clks = ARRAY_SIZE(msm8917_clks), + .power_domains = msm8917_gdscs, + .num_power_domains = ARRAY_SIZE(msm8917_gdscs), + + .enable = msm8917_enable, + .set_rate = msm8917_set_rate, +}; + +static const struct udevice_id gcc_msm8917_of_match[] = { + { + .compatible = "qcom,gcc-msm8917", + .data = (ulong)&msm8917_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_msm8917) = { + .name = "gcc_msm8917", + .id = UCLASS_NOP, + .of_match = gcc_msm8917_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; -- 2.55.0