Re: [PATCH v2 03/10] drm/i915/dp_mst: Limit M/N ratio for MST

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/dp_mst: mode_valid prunes modes on UHBR due to M/N ratio logic flaw
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commit d987781a69cc401d2c2bdee227fee0cfd510d97e
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/dp_mst: Limit M/N ratio for MST

This commit enforces the maximum M/N ratio limit for MST configurations in
mst_connector_mode_valid_ctx(), mirroring the SST path. It evaluates the
limit using the highest available link rate, dropping modes if the maximum
rate cannot support the required ratio.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 6a869d0f6ffc0..3f4ab9573d0c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
[ ... ]
> @@ -1564,6 +1565,15 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  					   min_link_bpp_x16,
>  					   bw_overhead_flags);
>  
> +	if (intel_dp_link_caps_get_max_config(intel_dp->link.caps,
> +					      INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
> +					      INTEL_DP_LINK_CAPS_FILTER_ALL,
> +					      &max_rate_config) &&
> +	    !intel_dp_can_support_m_n(display, mode->clock, max_rate_config.rate)) {

[Severity: Medium]
Will this logic incorrectly prune high pixel-clock display modes (like
4K@240Hz or 8K) on UHBR-capable displays?

The commit message states "the ratio shrinks as the link rate grows", but
when crossing from HBR3 (8.1 Gbps, 8b/10b, 10-bit symbol) to UHBR10 (10 Gbps,
128b/132b, 32-bit symbol), the symbol clock drops drastically.

Since the M/N ratio is proportional to pixel_clock / symbol_clock, evaluating
at the UHBR10 rate inflates the ratio. This might cause the ratio to exceed
the max limit (10) and fail here, even though the mode might have passed if
evaluated at HBR3.

Does this falsely prevent valid high-bandwidth modes from reaching the compute
config stage on modern DP 2.0/2.1 monitors?

> +		*status = MODE_CLOCK_HIGH;
> +		return 0;
> +	}
> +
>  	/*
>  	 * TODO:
>  	 * - Also check if compression would allow for the mode

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Sashiko AI review · https://sashiko.dev/#/patchset/20260916025710.432281-1-suraj.kandpal@intel.com?part=3