From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FF7936196D for ; Wed, 16 Sep 2026 14:49:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789570173; cv=none; b=HH7XzY1c1Opij9ll5uCLFm5/dxMYaypwfwJS64679tAjzntEWB42gfV9ARXzGGFKkt1nILBZ1feqB7nQ9oClbh47GbZyn+IOtXyjdGVVbWlY8fG1ZbZyBUWEWNbFmnFgygTOyweQBUTf9v67kn6apodC35meqbh8aBARGsOfe1I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789570173; c=relaxed/simple; bh=BvlaNWB8BCpGfil+ObifmT4ozXFEXm6qiKMmt3c5vv0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:content-type; b=QXjt1MW9E5vJIxRTbt5DYzYvfuOmo0MumjBQtqMx1eK8M27Aj6zVn3myHtFsJLK33WNPwFeNKazuuG4gsip8HZ5X+gr1LCvuEr3+TaiPqD9ktb8N5JIPbWq3RShElhwQ2YTwwjCJbgU2ZEiy0FmbQQKNG+NPtfrFZqRQdGlMzxI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=O/Nn9m7E; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="O/Nn9m7E" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1789570170; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QsdEaXja948buX+ojGX3SD8tUP4GCWVBkPrqyWvsMos=; b=O/Nn9m7EmKlS6EkapISvVBmY2YnkvQ+vGNFm+6t7v+wABm70MNzb7pV+BIpPBARFyoXouJ aP3tXcykjd+ughJNLuivOW9VGLTzt8RxeFwaGEiHQq5frgR9AC0Ub6Ib2bbeKygCS1Rrw8 GlauXZ25AnldbTQ/38ihn/20Oyj0Q7w= Received: from mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-681-bV4zK8U1O_muSRnRWq6-Yg-1; Wed, 16 Sep 2026 10:49:24 -0400 X-MC-Unique: bV4zK8U1O_muSRnRWq6-Yg-1 X-Mimecast-MFC-AGG-ID: bV4zK8U1O_muSRnRWq6-Yg_1789570162 Received: from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 8E94F1953941; Wed, 16 Sep 2026 14:49:22 +0000 (UTC) Received: from laptop.redhat.corp (headnet04.pony-001.prod.iad2.dc.redhat.com [10.2.32.116]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 7582119560AB; Wed, 16 Sep 2026 14:49:17 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v9 21/26] target/arm/kvm: add helper to test SYSREG props against a scratch vcpu Date: Wed, 16 Sep 2026 16:45:44 +0200 Message-ID: <20260916144721.751810-22-eric.auger@redhat.com> In-Reply-To: <20260916144721.751810-1-eric.auger@redhat.com> References: <20260916144721.751810-1-eric.auger@redhat.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 X-Mimecast-MFC-PROC-ID: qxPR_3QiFLpTRDY3knBAShJjIY9P8uYJZAvp_-A0ZOE_1789570162 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit content-type: text/plain; charset="US-ASCII"; x-default=true Add kvm_idreg_write_scratch_vcpu helper that will be used by qmp_query_cpu_model_expansion code to test SYSREG settings against a scratch vcpu. Indeed when the expansion code is called the actual vcpu has not been initialized so we use a scratch vcpu. This latter has been initialized with features taken from legacy compositive options (EL2, SVE, ...). So the trial is very close to the final setup. Signed-off-by: Eric Auger --- target/arm/kvm_arm.h | 4 ++++ target/arm/kvm-stub.c | 7 ++++++ target/arm/kvm.c | 51 +++++++++++++++++++++++++++++++++++++++++ target/arm/trace-events | 1 + 4 files changed, 63 insertions(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 2b3474cc36..bace69efed 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -14,6 +14,7 @@ #include "qapi/qapi-types-misc-arm.h" #include "system/kvm.h" #include "target/arm/cpu-qom.h" +#include "cpu-idregs.h" #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) @@ -250,4 +251,7 @@ void arm_gic_cap_kvm_probe(GICCapability *v2, GICCapability *v3); */ char *kvm_print_register_name(uint64_t regidx); +bool kvm_idreg_write_scratch_vcpu(ARMCPU *cpu, int cpufd, + ARM64SysRegField *field, uint64_t newfv, + Error **errp); #endif diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 88cbe8d85c..8e6fae0a4d 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -119,3 +119,10 @@ char *kvm_print_register_name(uint64_t regidx) { g_assert_not_reached(); } + +bool kvm_idreg_write_scratch_vcpu(ARMCPU *cpu, int cpufd, + ARM64SysRegField *field, uint64_t newfv, + Error **errp) +{ + g_assert_not_reached(); +} diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 537673177a..f7ca0e0250 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -447,6 +447,57 @@ static bool kvm_arm_vcpu_validate_sysreg(ARMCPU *cpu, ARM64SysRegField *field, #define KEY_TO_REG_IDX(key) ((uint32_t)(((uint64_t)(key)) >> 8)) #define KEY_TO_SHIFT(key) ((uint8_t)(((uint64_t)(key)) & 0xFF)) +bool kvm_idreg_write_scratch_vcpu(ARMCPU *cpu, int cpufd, + ARM64SysRegField *field, uint64_t newfv, + Error **errp) +{ + uint64_t mask, old_reg_val, new_reg_val, oldfv; + struct kvm_one_reg reg; + int lower = field->shift; + int length = field->length; + int index = field->index; + uint64_t kidx; + int ret; + + mask = MAKE_64BIT_MASK(lower, length); + + if (!kvm_arm_vcpu_validate_sysreg(cpu, field, newfv, errp)) { + return false; + }; + + kidx = idregs_sysreg_to_kvm_reg(id_register_sysreg[index]); + ret = read_sys_reg64(cpufd, &old_reg_val, kidx); + if (ret) { + error_setg(errp, "failed to read the scratch vcpu value for field %s %m", + field->name); + return false; + } + oldfv = (old_reg_val & mask) >> lower; + + new_reg_val = old_reg_val & ~mask; + new_reg_val |= newfv << lower; + + reg.id = kidx; + reg.addr = (uintptr_t)&new_reg_val; + ret = ioctl(cpufd, KVM_SET_ONE_REG, ®); + if (ret) { + error_setg(errp, "failed to apply new value 0x%"PRIx64" for field %s " + "(previous is 0x%"PRIx64"): %m", newfv, field->name, oldfv); + return false; + } else { + uint64_t check_val, actualfv; + + ret = read_sys_reg64(cpufd, &check_val, kidx); + if (ret) { + error_setg(errp, "failed to read the new reg value: %m"); + return false; + } + actualfv = (check_val & mask) >> lower; + trace_kvm_idreg_write_scratch_vcpu(field->name, oldfv, newfv, actualfv); + } + return true; +} + static void set_sysreg_prop(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) diff --git a/target/arm/trace-events b/target/arm/trace-events index 2a9cc67035..7a3f499a0e 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -21,6 +21,7 @@ set_sysreg_prop(const char *name, uint64_t old, uint64_t mask, uint64_t field_va apply_sysreg_prop(const char *reg_name, const char *field_name, uint64_t old, uint64_t current, uint64_t mask, uint64_t field_value, uint64_t new) "%s.%s old=0x%"PRIx64" current=0x%"PRIx64" mask=0x%"PRIx64" new field value=0x%"PRIx64" new=0x%"PRIx64 nb_sysreg_props(const char *name, int count) "%s: %d SYSREG properties" unexpected_writable_reserved_field(const char *reg_name, const char *field_name, int lower, int upper) "Unexpected writable reserved field: %s.%s [%d,%d], skip it ..." +kvm_idreg_write_scratch_vcpu(const char *name, uint64_t oldfv, uint64_t newfv, uint64_t actualfv) "successful dry-run for %s old=0x%"PRIx64" new=0x%"PRIx64" actual=0x%"PRIx64 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 -- 2.53.0