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[2003:f6:af00:a400:b6f5:2cb1:a2e8:9932]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4870bf33e01sm9655089f8f.23.2026.09.16.09.51.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Sep 2026 09:51:24 -0700 (PDT) From: Sebastian Ott To: Peter Maydell , Eric Auger , Jonathan Cameron , Alireza Sanaee , Richard Henderson , Cornelia Huck , khushit.shah@nutanix.com Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Eric Auger , Sebastian Ott Subject: [PATCH v6 1/3] arm: handle demuxed ID registers Date: Wed, 16 Sep 2026 18:51:15 +0200 Message-ID: <20260916165117.39764-2-sebott@redhat.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260916165117.39764-1-sebott@redhat.com> References: <20260916165117.39764-1-sebott@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: MkTFXezNUEomV_IaprujVozf3id7pRwAkzpUJrDtfZU_1789577485 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit content-type: text/plain; charset="US-ASCII"; x-default=true Received-SPF: pass client-ip=170.10.133.124; envelope-from=sebott@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org From: Cornelia Huck For some registers, we do not have a single ID register, but actually an array of values (e.g. CCSIDR_EL1, where the actual value is determined by whatever CSSELR_EL1 points to.) If we want to avoid using a different way to handle registers like that for every instance, we should provide some kind of infrastructure. Therefore, add accessors {GET,SET}_IDREG_DEMUX that are similar to the accessors we already use for regular ID registers. Tested-by: Alireza Sanaee Suggested-by: Richard Henderson Reviewed-by: Eric Auger Signed-off-by: Cornelia Huck Signed-off-by: Sebastian Ott --- target/arm/cpu-sysregs.h | 9 +++++++++ target/arm/cpu.h | 16 ++++++++++++++++ target/arm/cpu64.c | 8 ++++++++ 3 files changed, 33 insertions(+) diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h index 7877a3b06a..a4b9621a7e 100644 --- a/target/arm/cpu-sysregs.h +++ b/target/arm/cpu-sysregs.h @@ -20,20 +20,29 @@ #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX, +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ + NAME##_IDX, \ + NAME##_IDX_LAST = NAME##_IDX + NUM - 1, + typedef enum ARMIDRegisterIdx { #include "cpu-sysregs.h.inc" NUM_ID_IDX, } ARMIDRegisterIdx; #undef DEF +#undef DEF_MUX #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ SYS_##NAME = ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2), +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ + DEF(NAME, OP0, OP1, CRN, CRM, OP2) + typedef enum ARMSysRegs { #include "cpu-sysregs.h.inc" } ARMSysRegs; #undef DEF +#undef DEF_MUX extern const uint32_t id_register_sysreg[NUM_ID_IDX]; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e3f931dba2..6d1bad1dfc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -919,6 +919,22 @@ typedef struct { i_->idregs[REG ## _EL1_IDX]; \ }) +#define SET_IDREG_DEMUX(ISAR, REG, INDEX, VALUE) \ + ({ \ + ARMISARegisters *i_ = (ISAR); \ + unsigned int idx_ = REG ## _IDX + INDEX; \ + assert(idx_ <= REG ## _IDX_LAST); \ + i_->idregs[idx_] = VALUE; \ + }) + +#define GET_IDREG_DEMUX(ISAR, REG, INDEX) \ + ({ \ + ARMISARegisters *i_ = (ISAR); \ + unsigned int idx_ = REG ## _IDX + INDEX; \ + assert(idx_ <= REG ## _IDX_LAST); \ + i_->idregs[idx_]; \ + }) + /** * ARMCPU: * @env: #CPUARMState diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4e8c472530..c11ab2da21 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -42,14 +42,21 @@ #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ [NAME##_IDX] = SYS_##NAME, +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ + DEF(NAME, OP0, OP1, CRN, CRM, OP2) + const uint32_t id_register_sysreg[NUM_ID_IDX] = { #include "cpu-sysregs.h.inc" }; #undef DEF +#undef DEF_MUX #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ case SYS_##NAME: return NAME##_IDX; +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ + DEF(NAME, OP0, OP1, CRN, CRM, OP2) + int get_sysreg_idx(ARMSysRegs sysreg) { switch (sysreg) { @@ -59,6 +66,7 @@ int get_sysreg_idx(ARMSysRegs sysreg) } #undef DEF +#undef DEF_MUX void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { -- 2.55.0