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[2003:f6:af00:a400:b6f5:2cb1:a2e8:9932]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4870bf33e01sm9655089f8f.23.2026.09.16.09.51.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Sep 2026 09:51:26 -0700 (PDT) From: Sebastian Ott To: Peter Maydell , Eric Auger , Jonathan Cameron , Alireza Sanaee , Richard Henderson , Cornelia Huck , khushit.shah@nutanix.com Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Sebastian Ott Subject: [PATCH v6 3/3] arm/kvm: get demuxed ID registers from kvm Date: Wed, 16 Sep 2026 18:51:17 +0200 Message-ID: <20260916165117.39764-4-sebott@redhat.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260916165117.39764-1-sebott@redhat.com> References: <20260916165117.39764-1-sebott@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=sebott@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Cornelia Huck We now have the infrastructure in place to handle demuxed ID registers from kvm. Use it to get the values that kvm emulates for CCSIDR_EL1. Tested-by: Alireza Sanaee Signed-off-by: Cornelia Huck Signed-off-by: Sebastian Ott --- target/arm/kvm.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index ed99be7fd8..e4ef11945e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -244,6 +244,44 @@ static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, return ret; } + +/* CSSELR values supported by kvm; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ +#define KVM_CSSELR_MAX 14 +/* + * QEMU historically supported CSSELR values 0..15. This difference doen't matter + * since CSSELR_EL1.Level == 0b111 is reserved and thus CSSELR values 14..15 will + * make CCSIDR read as zero. Larger CSSELR values will only be necessary when + * support for MTE Allocation Tag caches is added. + */ +#define QEMU_CSSELR_MAX 16 + +static int get_host_cpu_reg_demux(int fd, ARMHostCPUFeatures *ahcf, + ARMIDRegisterIdx index, int subindex) +{ + + struct kvm_one_reg one_reg = { + .id = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX, + }; + + switch (index) { + case CCSIDR_EL1_IDX: + if (subindex >= QEMU_CSSELR_MAX) { + return -EINVAL; + } else if (subindex >= KVM_CSSELR_MAX) { + /* CSSELR_EL1.Level == 0b111 is reserved. */ + ahcf->isar.idregs[index + subindex] = 0; + return 0; + } + one_reg.id |= KVM_REG_ARM_DEMUX_ID_CCSIDR | subindex; + one_reg.addr = (uintptr_t)&ahcf->isar.idregs[index + subindex]; + break; + default: + return -EINVAL; + } + + return ioctl(fd, KVM_GET_ONE_REG, &one_reg); +} + static uint32_t kvm_arm_sve_get_vls(int fd) { uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; @@ -454,6 +492,10 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) /* Read the set of supported vector lengths. */ arm_host_cpu_features.sve_vq_supported = kvm_arm_sve_get_vls(fd); } + /* Grab demuxed registers. */ + for (int i = 0; i < QEMU_CSSELR_MAX; i++) { + err |= get_host_cpu_reg_demux(fd, ahcf, CCSIDR_EL1_IDX, i); + } } kvm_arm_destroy_scratch_host_vcpu(fdarray); -- 2.55.0