From: <mhonap@nvidia.com>
To: <alex@shazbot.org>, <jgg@ziepe.ca>, <ankita@nvidia.com>,
<jic23@kernel.org>, <dave.jiang@intel.com>,
<alejandro.lucero-palau@amd.com>, <smadhavan@nvidia.com>,
<corbet@lwn.net>, <skhan@linuxfoundation.org>,
<dave@stgolabs.net>, <alison.schofield@intel.com>,
<vishal.l.verma@intel.com>, <iweiny@kernel.org>,
<ming.li@zohomail.com>, <yishaih@nvidia.com>,
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<gustavoars@kernel.org>
Cc: <cjia@nvidia.com>, <kjaju@nvidia.com>, <vsethi@nvidia.com>,
<zhiw@nvidia.com>, <mhonap@nvidia.com>,
<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<kvm@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
<linux-pci@vger.kernel.org>, <linux-kselftest@vger.kernel.org>,
<linux-hardening@vger.kernel.org>
Subject: [PATCH v5 02/27] cxl/regs: Let a BAR-owning driver own the component register block
Date: Thu, 17 Sep 2026 00:05:15 +0530 [thread overview]
Message-ID: <20260916183540.3813685-3-mhonap@nvidia.com> (raw)
In-Reply-To: <20260916183540.3813685-1-mhonap@nvidia.com>
From: Manish Honap <mhonap@nvidia.com>
cxl_map_component_regs() claims each mapped sub-block with
devm_request_mem_region(). A driver that already requested the whole
component register BAR, such as vfio-cxl, would then collide with that
claim and fail to map the HDM decoder and RAS blocks.
Add cxl_reg_map_add_owned_resource() so such a driver records the
resource it already owns on the register map, and skip the sub-block
request when the block falls within an owned resource.
Assisted-by: LLM
Signed-off-by: Manish Honap <mhonap@nvidia.com>
---
drivers/cxl/core/regs.c | 17 +++++++++++++++--
include/cxl/cxl.h | 2 ++
include/cxl/pci.h | 3 +++
3 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index d79550dbb484..58a7c5cafb45 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -216,6 +216,13 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_iomap_block, "CXL");
+void cxl_reg_map_add_owned_resource(struct cxl_register_map *map,
+ struct resource *res)
+{
+ map->owned = res;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_reg_map_add_owned_resource, "CXL");
+
int cxl_map_component_regs(const struct cxl_register_map *map,
struct cxl_component_regs *regs,
unsigned long map_mask)
@@ -234,6 +241,7 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
struct mapinfo *mi = &mapinfo[i];
resource_size_t addr;
resource_size_t length;
+ struct resource res;
if (!mi->rmap->valid)
continue;
@@ -241,8 +249,13 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
continue;
addr = map->resource + mi->rmap->offset;
length = mi->rmap->size;
- *(mi->addr) = devm_cxl_iomap_block(host, addr, length);
- if (!*(mi->addr))
+ res = DEFINE_RES_MEM(addr, length);
+
+ if (map->owned && resource_contains(map->owned, &res))
+ *mi->addr = devm_cxl_ioremap_block(host, addr, length);
+ else
+ *mi->addr = devm_cxl_iomap_block(host, addr, length);
+ if (!*mi->addr)
return -ENOMEM;
}
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index a02792969e0a..92314f67b702 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -217,6 +217,7 @@ struct cxl_pmu_reg_map {
* @resource: physical resource base of the register block
* @max_size: maximum mapping size to perform register search
* @reg_type: see enum cxl_regloc_type
+ * @owned: driver-owned resource whose sub-blocks are mapped without re-requesting
* @component_map: cxl_reg_map for component registers
* @device_map: cxl_reg_maps for device registers
* @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units
@@ -227,6 +228,7 @@ struct cxl_register_map {
resource_size_t resource;
resource_size_t max_size;
u8 reg_type;
+ struct resource *owned;
union {
struct cxl_component_reg_map component_map;
struct cxl_device_reg_map device_map;
diff --git a/include/cxl/pci.h b/include/cxl/pci.h
index 3e0000015871..8e0b3bd0b3c1 100644
--- a/include/cxl/pci.h
+++ b/include/cxl/pci.h
@@ -16,7 +16,10 @@ enum cxl_regloc_type {
struct cxl_register_map;
struct pci_dev;
+struct resource;
int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
struct cxl_register_map *map);
+void cxl_reg_map_add_owned_resource(struct cxl_register_map *map,
+ struct resource *res);
#endif
--
2.25.1
next prev parent reply other threads:[~2026-09-16 18:37 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-16 18:35 [PATCH v5 00/27] vfio/pci: Add CXL Type-2 device passthrough support mhonap
2026-09-16 18:35 ` [PATCH v5 01/27] cxl/regs: Split the BAR block request and ioremap helpers mhonap
2026-09-22 1:28 ` Jonathan Cameron
2026-09-16 18:35 ` mhonap [this message]
2026-09-22 1:36 ` [PATCH v5 02/27] cxl/regs: Let a BAR-owning driver own the component register block Jonathan Cameron
2026-10-09 6:13 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 03/27] cxl: Move component register defines to uapi/cxl/cxl_regs.h mhonap
2026-09-22 1:43 ` Jonathan Cameron
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 04/27] cxl: Add cxl_reset_dvsec_sequence() for vfio-pci mhonap
2026-09-25 20:41 ` Jonathan Cameron
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 05/27] vfio/pci: Add the CXL provider ops registration interface mhonap
2026-09-16 18:35 ` [PATCH v5 06/27] vfio/pci: Detect CXL devices and load the CXL provider on demand mhonap
2026-09-17 8:48 ` Richard Cheng
2026-09-21 10:05 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 07/27] vfio/pci: Honor -EPROBE_DEFER from CXL provider probe mhonap
2026-09-16 18:35 ` [PATCH v5 08/27] vfio/pci: Fall back to plain vfio-pci when CXL init fails mhonap
2026-09-22 2:15 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 09/27] vfio/pci: Add a generic excluded-range list mhonap
2026-09-22 2:13 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-25 22:05 ` Jonathan Cameron
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 10/27] vfio/pci: Migrate MSI-X exclusion onto the " mhonap
2026-09-16 18:35 ` [PATCH v5 11/27] vfio/pci: Virtualize the CXL DVSEC in vfio_pci_config.c mhonap
2026-09-22 2:14 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-25 22:15 ` Jonathan Cameron
2026-10-09 6:15 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 12/27] vfio/pci: Call the CXL open and close hooks around device use mhonap
2026-09-25 22:17 ` Jonathan Cameron
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 13/27] vfio/pci: Bracket PCI resets with the CXL reset hooks mhonap
2026-09-22 2:14 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 14/27] vfio/pci: Provide an opt-out for the CXL Type-2 extensions mhonap
2026-09-16 18:35 ` [PATCH v5 15/27] vfio/cxl: Add the vfio-cxl provider module skeleton mhonap
2026-09-16 18:35 ` [PATCH v5 16/27] vfio/cxl: Create the CXL memdev and set media ready at bind mhonap
2026-09-22 2:14 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-25 22:22 ` Jonathan Cameron
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 17/27] vfio/cxl: Own the whole component register BAR mhonap
2026-09-22 2:14 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 18/27] vfio/cxl: Expose the HDM memory region to the guest mhonap
2026-09-22 2:14 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 19/27] vfio/cxl: Contain HDM memory errors with memory_failure() mhonap
2026-09-16 18:35 ` [PATCH v5 20/27] vfio/cxl: Expose the HDM decoder registers read-only to the guest mhonap
2026-09-22 2:13 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 21/27] vfio/cxl: Exclude the HDM decoder registers from direct BAR access mhonap
2026-09-17 7:28 ` Richard Cheng
2026-09-21 9:52 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 22/27] vfio/cxl: Clear the HDM access gate after a hot reset mhonap
2026-09-22 2:13 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 23/27] vfio/cxl: Describe the CXL device and decoder geometry to userspace mhonap
2026-09-16 18:35 ` [PATCH v5 24/27] vfio/cxl: Export the HDM memory region as a dma-buf mhonap
2026-09-17 7:55 ` Richard Cheng
2026-09-21 9:58 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 25/27] vfio/cxl: Run the CXL reset at the vfio reset points mhonap
2026-09-17 8:11 ` Richard Cheng
2026-09-21 10:01 ` Manish Honap
2026-09-22 2:13 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 26/27] Documentation: vfio-pci: Document CXL Type-2 device passthrough mhonap
2026-09-16 19:33 ` Gregory Price
2026-09-21 9:43 ` Manish Honap
2026-09-24 0:54 ` Jonathan Cameron
2026-10-09 6:15 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 27/27] selftests/vfio: Add CXL Type-2 passthrough tests mhonap
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