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[80.230.79.236]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4870bf462cesm16370722f8f.37.2026.09.17.10.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Sep 2026 10:17:05 -0700 (PDT) Date: Thu, 17 Sep 2026 13:17:02 -0400 From: "Michael S. Tsirkin" To: lirongqing Cc: qemu-devel@nongnu.org Subject: Re: [PATCH] pcie_sriov: fix wrong write width and off-by-one in pf_reset Message-ID: <20260917131304-mutt-send-email-mst@kernel.org> References: <20260917053818.2565-1-lirongqing@baidu.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260917053818.2565-1-lirongqing@baidu.com> Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Sep 17, 2026 at 01:38:18PM +0800, lirongqing wrote: > From: Li RongQing > > pcie_sriov_pf_reset() restores the VF BAR type registers using > pci_set_quad() with a 4-byte stride. Since each VF BAR register is > 4 bytes wide, the 8-byte write also covers the following BAR > register. Although subsequent iterations overwrite most of the > unintended writes, the access is incorrect and the final iteration > can write beyond the VF BAR registers. > > SR-IOV defines six VF BAR registers and does not provide a VF ROM BAR. > However, several SR-IOV code paths use PCI_NUM_REGIONS, which includes > the ROM slot and therefore has a value of seven. > > In particular, the final iteration in pcie_sriov_pf_reset() currently > writes a quadword at the offset of the seventh region. This starts at > the byte immediately following the six VF BAR registers and can > overwrite subsequent fields in the SR-IOV capability. > > Use pci_set_long() to match the 4-byte VF BAR register width, and use > PCI_SRIOV_NUM_BARS when iterating over SR-IOV VF BARs. This also makes > the BAR count consistent with the assertion in > pcie_sriov_pf_init_vf_bar(). > > Fixes: 7c0fa8dff811b5 ("pcie: Add support for Single Root I/O Virtualization (SR/IOV)") i do not see the bug in that version. do u mean 19e55471d4e8 maybe? > Fixes: c8bc4db403e176 ("pcie_sriov: Reset SR-IOV extended capability") > Signed-off-by: Li RongQing > --- > hw/pci/pcie_sriov.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c > index c41ac95..6122a26 100644 > --- a/hw/pci/pcie_sriov.c > +++ b/hw/pci/pcie_sriov.c > @@ -229,7 +229,7 @@ void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, > > assert(sriov_cap > 0); > assert(region_num >= 0); > - assert(region_num < PCI_NUM_REGIONS); > + assert(region_num < PCI_SRIOV_NUM_BARS); > assert(region_num != PCI_ROM_SLOT); > > wmask = ~(size - 1); > @@ -308,7 +308,7 @@ int16_t pcie_sriov_pf_init_from_user_created_vfs(PCIDevice *dev, > return -1; > } > > - for (size_t j = 0; j < PCI_NUM_REGIONS; j++) { > + for (size_t j = 0; j < PCI_SRIOV_NUM_BARS; j++) { > if (vfs[i]->io_regions[j].size != vfs[0]->io_regions[j].size || > vfs[i]->io_regions[j].type != vfs[0]->io_regions[j].type) { > error_setg(errp, "inconsistent SR-IOV BARs"); > @@ -344,7 +344,7 @@ int16_t pcie_sriov_pf_init_from_user_created_vfs(PCIDevice *dev, > dev->exp.sriov_pf.vf = vfs; > dev->exp.sriov_pf.vf_user_created = true; > > - for (i = 0; i < PCI_NUM_REGIONS; i++) { > + for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { > PCIIORegion *region = &vfs[0]->io_regions[i]; > > if (region->size) { > @@ -463,8 +463,8 @@ void pcie_sriov_pf_reset(PCIDevice *dev) > */ > pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); > > - for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) { > - pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, > + for (uint16_t i = 0; i < PCI_SRIOV_NUM_BARS; i++) { > + pci_set_long(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, > dev->exp.sriov_pf.vf_bar_type[i]); > } > } > -- > 2.9.4