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[159.2.239.150]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-9123bec59fasm50600486d6.39.2026.09.17.07.02.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Sep 2026 07:02:54 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1x7ChR-0000000Co7R-3O0W; Thu, 17 Sep 2026 11:02:53 -0300 Date: Thu, 17 Sep 2026 11:02:53 -0300 From: Jason Gunthorpe To: Thomas =?utf-8?Q?Hellstr=C3=B6m?= Cc: Leon Romanovsky , Bjorn Helgaas , Logan Gunthorpe , Chaitanya Kulkarni , Greg Kroah-Hartman , Jens Axboe , Alex Williamson , Ankit Agrawal , Jonathan Corbet , Shuah Khan , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Randy Dunlap , Sumit Semwal , Christian =?utf-8?B?S8O2bmln?= , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, iommu@lists.linux.dev, Tushar Dave , linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org, linux-rdma@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH v6 18/18] RDMA/mlx5: Ask P2PDMA whether ATS takes a direct peer-to-peer route Message-ID: <20260917140253.GG3196566@ziepe.ca> References: <20260914-fix-p2p-acs-v4-0-v6-0-5ef07ec9ef06@nvidia.com> <20260914-fix-p2p-acs-v4-0-v6-18-5ef07ec9ef06@nvidia.com> <321890690ce83d1943b2f678bd9bee9b8c895b66.camel@linux.intel.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <321890690ce83d1943b2f678bd9bee9b8c895b66.camel@linux.intel.com> On Thu, Sep 17, 2026 at 03:56:12PM +0200, Thomas Hellström wrote: > That is, a flag to tell the topology check that some transactions > *will* take the host-bridge path due to IOVA being used, and that the > computations including pci_p2pdma_distance() need to check whether that > is possible (checking whitelist etc.) and return the corresponding > THRU_HOST_BRIDGE mapping type. Translated transactions taking a short- > cut using the bus-address would then be hidden from the driver. I imagined it would work by the driver passing in what modes it supports and Intel GPU would simply pass in ATS only. Even something like mlx has variation, only some operations can opt into ATS, many others are never-ATS. Driver should not make statements like " *will* take the host-bridge path" since it has no idea. Jason