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Fri, 18 Sep 2026 06:53:50 +0000 From: Kane Chen To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Troy Lee , Kane Chen Subject: [PATCH v2 2/3] hw/misc/aspeed_sbc: Derive ABR state from OTP config straps Thread-Topic: [PATCH v2 2/3] hw/misc/aspeed_sbc: Derive ABR state from OTP config straps Thread-Index: AQHdRzp2ulw00Hg0h0Gv5ZmgRF7wwg== Date: Fri, 18 Sep 2026 06:53:50 +0000 Message-ID: <20260918065347.3713868-3-kane_chen@aspeedtech.com> References: <20260918065347.3713868-1-kane_chen@aspeedtech.com> In-Reply-To: <20260918065347.3713868-1-kane_chen@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SEZPR06MB7619:EE_|SEZPR06MB8814:EE_ x-ms-office365-filtering-correlation-id: 2a99ac63-406e-4d43-179d-08df15519899 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=kane_chen@aspeedtech.com; helo=TYDPR03CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The eMMC ABR enable state is currently controlled by the "emmc-abr"=0A= machine property instead of the OTP configuration.=0A= =0A= Add helpers to read the OTP configuration and resolve strap values.=0A= Use the ABR strap value to update ABR_EN when R_STATUS is read.=0A= =0A= Remove the "emmc-abr" property as the ABR state is now derived from=0A= OTP.=0A= =0A= Signed-off-by: Kane-Chen-AS =0A= ---=0A= include/hw/misc/aspeed_sbc.h | 1 -=0A= include/hw/nvram/aspeed_otp.h | 23 +++++++++++--=0A= hw/misc/aspeed_sbc.c | 29 ++++++++++++----=0A= hw/nvram/aspeed_otp.c | 63 +++++++++++++++++++++++++++++++++++=0A= 4 files changed, 106 insertions(+), 10 deletions(-)=0A= =0A= diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h=0A= index 756c612356..b210ffb8aa 100644=0A= --- a/include/hw/misc/aspeed_sbc.h=0A= +++ b/include/hw/misc/aspeed_sbc.h=0A= @@ -32,7 +32,6 @@ OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEE= D_SBC)=0A= struct AspeedSBCState {=0A= SysBusDevice parent;=0A= =0A= - bool emmc_abr;=0A= uint32_t signing_settings;=0A= =0A= MemoryRegion iomem;=0A= diff --git a/include/hw/nvram/aspeed_otp.h b/include/hw/nvram/aspeed_otp.h= =0A= index 2b6c2eaaa3..f91af12ea9 100644=0A= --- a/include/hw/nvram/aspeed_otp.h=0A= +++ b/include/hw/nvram/aspeed_otp.h=0A= @@ -24,11 +24,27 @@ OBJECT_DECLARE_SIMPLE_TYPE(AspeedOTPState, ASPEED_OTP)= =0A= *=0A= * - [0, OTP_DATA_DWORD_COUNT]: the data region. Each address contains=0A= * 64 bits of data.=0A= - * - [OTP_DATA_DWORD_COUNT, OTP_MEMORY_SIZE / 4]: the configuration=0A= - * region. Each address contains 32 bits of data.=0A= + * - [OTP_DATA_DWORD_COUNT(OTP_CFG0), OTP_MEMORY_SIZE / 4]: the=0A= + * configuration region. Each address contains 32 bits of data.=0A= */=0A= #define OTP_DATA_DWORD_COUNT (0x800)=0A= =0A= +/* Start of the OTP configuration/strap region. */=0A= +#define OTP_CFG0 (0x800)=0A= +=0A= +/*=0A= + * OTP straps are a 64-bit value packed as two 32-bit halves starting at= =0A= + * config word OTP_STRAP_START_INDEX (OTPCFG16 and OTPCFG17). Each strap= =0A= + * bit is stored redundantly in OTP_STRAP_COPY_NUM config words, spaced=0A= + * (OTP_STRAP_BIT_NUM / 32) words apart -- i.e. one word per 32-bit half,= =0A= + * so the two halves interleave; the effective bit value is the XOR of=0A= + * all copies, matching how the real hardware and the ast-otp reference=0A= + * tool resolve straps.=0A= + */=0A= +#define OTP_STRAP_START_INDEX 16=0A= +#define OTP_STRAP_BIT_NUM 64=0A= +#define OTP_STRAP_COPY_NUM 6=0A= +=0A= typedef struct AspeedOTPState {=0A= DeviceState parent_obj;=0A= =0A= @@ -43,4 +59,7 @@ typedef struct AspeedOTPState {=0A= uint8_t *storage;=0A= } AspeedOTPState;=0A= =0A= +uint32_t aspeed_otp_read_config(AspeedOTPState *s, unsigned int cfg_word);= =0A= +bool aspeed_otp_read_strap(AspeedOTPState *s, unsigned int bit);=0A= +=0A= #endif /* ASPEED_OTP_H */=0A= diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c=0A= index 3402cef5c3..6cec9ad3da 100644=0A= --- a/hw/misc/aspeed_sbc.c=0A= +++ b/hw/misc/aspeed_sbc.c=0A= @@ -71,6 +71,9 @@=0A= #define SBC_OTP_CMD_WRITE 0x23b1e362=0A= #define SBC_OTP_CMD_PROG 0x23b1e364=0A= =0A= +/* OTP strap bits */=0A= +#define OTP_STRAP_ABR_EN 0x2b=0A= +=0A= /* Voltage mode */=0A= #define MODE_REGISTER (0x1000)=0A= #define MODE_REGISTER_A (0x3000)=0A= @@ -89,7 +92,21 @@ static uint64_t aspeed_sbc_read(void *opaque, hwaddr add= r, unsigned int size)=0A= return 0;=0A= }=0A= =0A= - return s->regs[addr];=0A= + switch (addr) {=0A= + case R_STATUS: {=0A= + uint32_t val =3D s->regs[R_STATUS];=0A= +=0A= + if (aspeed_otp_read_strap(&s->otp, OTP_STRAP_ABR_EN)) {=0A= + val |=3D ABR_EN;=0A= + } else {=0A= + val &=3D ~ABR_EN;=0A= + }=0A= +=0A= + return val;=0A= + }=0A= + default:=0A= + return s->regs[addr];=0A= + }=0A= }=0A= =0A= static bool aspeed_otp_read(AspeedSBCState *s, uint32_t otp_addr,=0A= @@ -388,13 +405,12 @@ static void aspeed_sbc_reset_hold(Object *obj, ResetT= ype type)=0A= =0A= memset(s->regs, 0, sizeof(s->regs));=0A= =0A= - /* Set secure boot enabled with RSA4096_SHA256 and enable eMMC ABR */= =0A= + /*=0A= + * ABR_EN is derived from OTP on every read, see aspeed_sbc_read().=0A= + * Set secure boot enabled with RSA4096_SHA256.=0A= + */=0A= s->regs[R_STATUS] =3D OTP_IDLE | OTP_MEM_IDLE;=0A= =0A= - if (s->emmc_abr) {=0A= - s->regs[R_STATUS] &=3D ABR_EN;=0A= - }=0A= -=0A= if (s->signing_settings) {=0A= s->regs[R_STATUS] &=3D SECURE_BOOT_EN;=0A= }=0A= @@ -452,7 +468,6 @@ static const VMStateDescription vmstate_aspeed_sbc =3D = {=0A= };=0A= =0A= static const Property aspeed_sbc_properties[] =3D {=0A= - DEFINE_PROP_BOOL("emmc-abr", AspeedSBCState, emmc_abr, 0),=0A= DEFINE_PROP_UINT32("signing-settings", AspeedSBCState, signing_setting= s, 0),=0A= DEFINE_PROP_LINK("sram", AspeedSBCState, sram,=0A= TYPE_MEMORY_REGION, MemoryRegion *),=0A= diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c=0A= index 81304bda3a..127da15642 100644=0A= --- a/hw/nvram/aspeed_otp.c=0A= +++ b/hw/nvram/aspeed_otp.c=0A= @@ -106,6 +106,69 @@ static void aspeed_otp_write(void *opaque, hwaddr otp_= offset,=0A= trace_aspeed_otp_prog(otp_offset, val, value);=0A= }=0A= =0A= +/*=0A= + * Each OTP configuration setting contains 32 bits of data.=0A= + * Configuration words are grouped in banks of 8, with banks spaced=0A= + * 0x200 dwords apart and words within a bank spaced 2 dwords apart:=0A= + *=0A= + * offset(n) =3D OTP_CFG0 + (n / 8) * 0x200 + (n % 8) * 2=0A= + *=0A= + * Returns 0 if the OTP read fails.=0A= + */=0A= +uint32_t aspeed_otp_read_config(AspeedOTPState *s, unsigned int cfg_word)= =0A= +{=0A= + uint32_t otp_addr =3D OTP_CFG0 + (cfg_word / 8) * 0x200 + (cfg_word % = 8) * 2;=0A= + uint32_t value =3D 0;=0A= +=0A= + if (address_space_read(&s->as, otp_addr << 2, MEMTXATTRS_UNSPECIFIED,= =0A= + &value, sizeof(value)) !=3D MEMTX_OK) {=0A= + qemu_log_mask(LOG_GUEST_ERROR,=0A= + "%s: Failed to read OTP config word %u\n",=0A= + __func__, cfg_word);=0A= + return 0;=0A= + }=0A= +=0A= + return value;=0A= +}=0A= +=0A= +/*=0A= + * OTP straps are a 64-bit value split across two 32-bit config words,=0A= + * each of which is repeated OTP_STRAP_COPY_NUM times for reliability.=0A= + * The two words interleave starting at OTP_STRAP_START_INDEX:=0A= + *=0A= + * cfg_word: 16 17 18 19 20 21 22 23 24 25 26 2= 7=0A= + * +----+----+----+----+----+----+----+----+----+----+----+--= --+=0A= + * | L0 | H0 | L1 | H1 | L2 | H2 | L3 | H3 | L4 | H4 | L5 | H= 5 |=0A= + * +----+----+----+----+----+----+----+----+----+----+----+--= --+=0A= + *=0A= + * Lx =3D copy #x of bit 0-31, Hx =3D copy #x of bit 32-63=0A= + * (x =3D 0 .. OTP_STRAP_COPY_NUM - 1)=0A= + *=0A= + * To resolve strap bit `n` (0 <=3D n < OTP_STRAP_BIT_NUM):=0A= + * half =3D n / 32 -- 0 selects the L* words, 1 selects the H* word= s=0A= + * bit_pos =3D n % 32 -- bit position within the word=0A= + * word(i) =3D OTP_STRAP_START_INDEX + half + i * (OTP_STRAP_BIT_NUM / 3= 2)=0A= + *=0A= + * The effective value of bit `n` is the XOR of bit `bit_pos` across all= =0A= + * OTP_STRAP_COPY_NUM copies of word(i).=0A= + */=0A= +bool aspeed_otp_read_strap(AspeedOTPState *s, unsigned int bit)=0A= +{=0A= + uint32_t cfg_word =3D OTP_STRAP_START_INDEX + bit / 32;=0A= + uint32_t bit_pos =3D bit % 32;=0A= + bool enable =3D false;=0A= + int i;=0A= +=0A= + assert(bit < OTP_STRAP_BIT_NUM);=0A= +=0A= + for (i =3D 0; i < OTP_STRAP_COPY_NUM; i++) {=0A= + enable ^=3D (aspeed_otp_read_config(s, cfg_word) >> bit_pos) & 0x1= ;=0A= + cfg_word +=3D OTP_STRAP_BIT_NUM / 32;=0A= + }=0A= +=0A= + return enable;=0A= +}=0A= +=0A= static bool aspeed_otp_init_storage(AspeedOTPState *s, Error **errp)=0A= {=0A= uint32_t *p;=0A= -- =0A= 2.43.0=0A=