Re: [PATCH v2 8/8] arm64: dts: renesas: r9a08g046: Enable TSU

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dt: io-channels hardcodes Linux array index instead of hardware ID
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commit 43dcf56f74f46f025839610adda743ab502b8711
Author: Biju Das <biju.das.jz@bp.renesas.com>
arm64: dts: renesas: r9a08g046: Enable TSU

This commit adds cooling cells to the CPU nodes and describes the ADC1 and TSU
nodes to enable thermal mitigation. It also sets up a CPU thermal zone with
passive and critical trip points.

> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> index c63a857f0e5b0..a2f6718c0043a 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
[ ... ]
> +		adc1: adc@108c0000 {
> +			compatible = "renesas,r9a08g046-adc1";
> +			reg = <0 0x108c0000 0 0x10000>;
> +			interrupts = <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>;
> +			clocks = <&cpg CPG_MOD R9A08G046_ADC1_ADCLK>,
> +				 <&cpg CPG_MOD R9A08G046_ADC1_PCLK>;
> +			clock-names = "adclk", "pclk";
> +			resets = <&cpg R9A08G046_ADC1_PRESETN>,
> +				 <&cpg R9A08G046_ADC1_ADRST_N>;
> +			reset-names = "presetn", "adrst-n";
> +			power-domains = <&cpg>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			#io-channel-cells = <1>;
> +
> +			channel@8 {
> +				reg = <8>;
> +			};
> +		};
> +
> +		tsu: thermal@108d0000 {
> +			compatible = "renesas,r9a08g046-tsu";
> +			reg = <0 0x108d0000 0 0x10000>;
> +			clocks = <&cpg CPG_MOD R9A08G046_TSU_PCLK>;
> +			resets = <&cpg R9A08G046_TSU_PRESETN>;
> +			power-domains = <&cpg>;
> +			#thermal-sensor-cells = <0>;
> +			io-channels = <&adc1 0>;
> +			io-channel-names = "tsu";

[Severity: Medium]
Does this hardcode an internal Linux array index (0) instead of the actual
hardware channel ID (8)?

Since channel@8 is the only defined channel in the adc1 node, it currently
sits at index 0 in the driver's array, which masks the issue.

If a future device tree update enables another channel (like channel@0),
would the array shift so index 0 points to the wrong physical channel? This
looks like it could cause the CPU to read incorrect thermal data and break
thermal mitigation.

> +		};

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Sashiko AI review · https://sashiko.dev/#/patchset/20260918150730.122056-1-biju.das.jz@bp.renesas.com?part=8