[PULL 0/4] Linux user patches

[Helge Deller <deller@kernel.org>]

From: Helge Deller <deller@gmx.de>

The following changes since commit e8dca265c91b45f4cde746e5094d7b763444eb6a:

  Merge tag 'pull-11.1-more-check-tcg-docker-meson-180926-1' of https://gitlab.com/stsquad/qemu into staging (2026-09-18 07:52:24 -1000)

are available in the Git repository at:

  https://github.com/hdeller/qemu-hppa.git tags/linux-user-pull-request

for you to fetch changes up to e95f53e30be7935d98e38eb09cd6360fe2886249:

  linux-user/loongarch64: Detect vector stores in host_signal_write() (2026-09-18 22:20:21 +0200)

----------------------------------------------------------------
linux-user patches for mlock syscall and loongarch64 and riscv fixes

Add support for the mlock syscall, and some fixes for loongarch64 and riscv.

----------------------------------------------------------------

Michael Morrell (1):
  linux-user: implement mlock2(2) syscall

SignKirigami (1):
  linux-user/loongarch64: Detect vector stores in host_signal_write()

wangyang (2):
  linux-user/riscv: honor zicntr=false for base counterCSRs
  linux-user/riscv: invalidate reservations after stores

 .../include/host/loongarch64/host-signal.h    |  6 +++
 linux-user/riscv/target_cpu.h                 |  2 +
 linux-user/syscall.c                          |  9 +++++
 linux-user/syscall_defs.h                     |  4 ++
 target/riscv/cpu.c                            |  3 ++
 target/riscv/cpu.h                            |  3 ++
 target/riscv/helper.h                         |  5 +++
 target/riscv/tcg/csr.c                        | 11 ++++--
 target/riscv/tcg/insn_trans/trans_rva.c.inc   | 24 ++++++++++++
 target/riscv/tcg/insn_trans/trans_rvi.c.inc   | 11 ++++++
 .../riscv/tcg/insn_trans/trans_rvzawrs.c.inc  |  3 ++
 target/riscv/tcg/op_helper.c                  | 35 +++++++++++++++++
 target/riscv/tcg/translate.c                  | 38 +++++++++++++++++++
 13 files changed, 150 insertions(+), 4 deletions(-)

-- 
2.54.0