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Sun, 20 Sep 2026 07:16:24 -0700 (PDT) Received: from [127.0.1.1] ([151.51.151.34]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fc57547easm184107005e9.3.2026.09.20.07.16.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 07:16:24 -0700 (PDT) Sender: Massimo Pegorer From: Massimo Pegorer Date: Sun, 20 Sep 2026 16:15:49 +0200 Subject: [PATCH RFC 05/11] arm: rockchip: support DISPLAY_CPUINFO on all Rockchip SoC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260920-reset-v1-5-42820216369f@gmail.com> References: <20260920-reset-v1-0-42820216369f@gmail.com> In-Reply-To: <20260920-reset-v1-0-42820216369f@gmail.com> To: Simon Glass , Quentin Schulz , u-boot@lists.u-boot-project.org Cc: Tom Rini , Ilias Apalodimas , Kever Yang , Lukasz Majewski , Anatolij Gustschin , Heiko Schocher , Marek Vasut , Svyatoslav Ryhel , Peter Robinson , Levin Du , Suniel Mahesh , Alexey Charkov , Fabio Estevam , Jonas Karlman , Chris Morgan , Coia Prant , Frank Wunderlich , Andy Yan , Liangbin Lian , Joseph Chen , Tianling Shen , Klaus Goger , Heiko Stuebner , Jacobe Zang , Jiehui He , John Clark , Sebastian Kropatsch , Jagan Teki , Ilya Katsnelson , Niu Zhihong , Nicolas Frattaroli , Tom Fitzhenry , Akash Gajjar , Maxim Moskalets , FUKAUMI Naoki , Eugen Hristev , Jianfeng Liu , Elon Zhang , Joshua Riek , Martin Herren , Torsten Duwe , Massimo Pegorer X-Mailer: b4 0.15.2 X-Mailman-Approved-At: Sun, 20 Sep 2026 15:49:13 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Move rockchip_get_reset_cause() implementation to SoC-specific source files, leaving a dummy weak common implementation in cpu-info.c file: an effective common implementation is not feasible due SoC differences. BTW the existing ones for RK3568 and RK3588 need to be fixed/improved because their CRU_GLB_RST_ST registers differ from the one common to RK3288 and RK3399 on which the implementation is based. Moreover, now all the Rockchip SoC board configurations can select the DISPLAY_CPUINFO config option and compile cpu-info.c successfully which provides print_cpuinfo(). Previously, boards with SoC other than RK3288 RK3399 RK3568 and RK3588 could not have DISPLAY_CPUINFO selected. Signed-off-by: Massimo Pegorer --- arch/arm/mach-rockchip/cpu-info.c | 44 ++---------------------------- arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 35 ++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 35 ++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3568/clk_rk3568.c | 35 ++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3588/clk_rk3588.c | 35 ++++++++++++++++++++++++ 5 files changed, 142 insertions(+), 42 deletions(-) diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index 2ec96a20c3d..b6e3d9ff964 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -10,49 +10,9 @@ #include #include -#if defined(CONFIG_ROCKCHIP_RK3288) -# include -#elif defined(CONFIG_ROCKCHIP_RK3399) -# include -#elif defined(CONFIG_ROCKCHIP_RK3568) -#include -#elif defined(CONFIG_ROCKCHIP_RK3588) -#include -#endif - -/* CRU_GLB_RST_ST */ -enum { - GLB_POR_RST, - FST_GLB_RST_ST = BIT(0), - SND_GLB_RST_ST = BIT(1), - FST_GLB_TSADC_RST_ST = BIT(2), - SND_GLB_TSADC_RST_ST = BIT(3), - FST_GLB_WDT_RST_ST = BIT(4), - SND_GLB_WDT_RST_ST = BIT(5), -}; - -enum rockchip_rst_cause rockchip_get_reset_cause(void) +__weak enum rockchip_rst_cause rockchip_get_reset_cause(void) { - struct rockchip_cru *cru = rockchip_get_cru(); - - if (IS_ERR(cru)) - return RST_CAUSE_UNAVAILABLE; - - switch (cru->glb_rst_st) { - case GLB_POR_RST: - return RST_CAUSE_POR; - case FST_GLB_RST_ST: - case SND_GLB_RST_ST: - return RST_CAUSE_REG; - case FST_GLB_TSADC_RST_ST: - case SND_GLB_TSADC_RST_ST: - return RST_CAUSE_THERMAL; - case FST_GLB_WDT_RST_ST: - case SND_GLB_WDT_RST_ST: - return RST_CAUSE_WDOG; - } - - return RST_CAUSE_UNKNOWN; + return RST_CAUSE_UNAVAILABLE; } #if IS_ENABLED(CONFIG_DISPLAY_CPUINFO) diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c index d725730f5bd..a245d865a0b 100644 --- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c @@ -30,3 +30,38 @@ void *rockchip_get_cru(void) return priv->cru; } + +/* CRU_GLB_RST_ST */ +enum { + GLB_POR_RST, + FST_GLB_RST_ST = BIT(0), + SND_GLB_RST_ST = BIT(1), + FST_GLB_TSADC_RST_ST = BIT(2), + SND_GLB_TSADC_RST_ST = BIT(3), + FST_GLB_WDT_RST_ST = BIT(4), + SND_GLB_WDT_RST_ST = BIT(5), +}; + +enum rockchip_rst_cause rockchip_get_reset_cause(void) +{ + struct rockchip_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return RST_CAUSE_UNAVAILABLE; + + switch (cru->glb_rst_st) { + case GLB_POR_RST: + return RST_CAUSE_POR; + case FST_GLB_RST_ST: + case SND_GLB_RST_ST: + return RST_CAUSE_REG; + case FST_GLB_TSADC_RST_ST: + case SND_GLB_TSADC_RST_ST: + return RST_CAUSE_THERMAL; + case FST_GLB_WDT_RST_ST: + case SND_GLB_WDT_RST_ST: + return RST_CAUSE_WDOG; + } + + return RST_CAUSE_UNKNOWN; +} diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index 170071d243d..afd57b2e354 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -51,3 +51,38 @@ void *rockchip_get_pmucru(void) return priv->pmucru; } + +/* CRU_GLB_RST_ST */ +enum { + GLB_POR_RST, + FST_GLB_RST_ST = BIT(0), + SND_GLB_RST_ST = BIT(1), + FST_GLB_TSADC_RST_ST = BIT(2), + SND_GLB_TSADC_RST_ST = BIT(3), + FST_GLB_WDT_RST_ST = BIT(4), + SND_GLB_WDT_RST_ST = BIT(5), +}; + +enum rockchip_rst_cause rockchip_get_reset_cause(void) +{ + struct rockchip_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return RST_CAUSE_UNAVAILABLE; + + switch (cru->glb_rst_st) { + case GLB_POR_RST: + return RST_CAUSE_POR; + case FST_GLB_RST_ST: + case SND_GLB_RST_ST: + return RST_CAUSE_REG; + case FST_GLB_TSADC_RST_ST: + case SND_GLB_TSADC_RST_ST: + return RST_CAUSE_THERMAL; + case FST_GLB_WDT_RST_ST: + case SND_GLB_WDT_RST_ST: + return RST_CAUSE_WDOG; + } + + return RST_CAUSE_UNKNOWN; +} diff --git a/arch/arm/mach-rockchip/rk3568/clk_rk3568.c b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c index 1c6b2ece602..e10bcef727d 100644 --- a/arch/arm/mach-rockchip/rk3568/clk_rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c @@ -50,3 +50,38 @@ void *rockchip_get_pmucru(void) return priv->pmucru; } + +/* CRU_GLB_RST_ST */ +enum { + GLB_POR_RST, + FST_GLB_RST_ST = BIT(0), + SND_GLB_RST_ST = BIT(1), + FST_GLB_TSADC_RST_ST = BIT(2), + SND_GLB_TSADC_RST_ST = BIT(3), + FST_GLB_WDT_RST_ST = BIT(4), + SND_GLB_WDT_RST_ST = BIT(5), +}; + +enum rockchip_rst_cause rockchip_get_reset_cause(void) +{ + struct rockchip_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return RST_CAUSE_UNAVAILABLE; + + switch (cru->glb_rst_st) { + case GLB_POR_RST: + return RST_CAUSE_POR; + case FST_GLB_RST_ST: + case SND_GLB_RST_ST: + return RST_CAUSE_REG; + case FST_GLB_TSADC_RST_ST: + case SND_GLB_TSADC_RST_ST: + return RST_CAUSE_THERMAL; + case FST_GLB_WDT_RST_ST: + case SND_GLB_WDT_RST_ST: + return RST_CAUSE_WDOG; + } + + return RST_CAUSE_UNKNOWN; +} diff --git a/arch/arm/mach-rockchip/rk3588/clk_rk3588.c b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c index 250ec423bd2..5698b16db58 100644 --- a/arch/arm/mach-rockchip/rk3588/clk_rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c @@ -29,3 +29,38 @@ void *rockchip_get_cru(void) return priv->cru; } + +/* CRU_GLB_RST_ST */ +enum { + GLB_POR_RST, + FST_GLB_RST_ST = BIT(0), + SND_GLB_RST_ST = BIT(1), + FST_GLB_TSADC_RST_ST = BIT(2), + SND_GLB_TSADC_RST_ST = BIT(3), + FST_GLB_WDT_RST_ST = BIT(4), + SND_GLB_WDT_RST_ST = BIT(5), +}; + +enum rockchip_rst_cause rockchip_get_reset_cause(void) +{ + struct rockchip_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return RST_CAUSE_UNAVAILABLE; + + switch (cru->glb_rst_st) { + case GLB_POR_RST: + return RST_CAUSE_POR; + case FST_GLB_RST_ST: + case SND_GLB_RST_ST: + return RST_CAUSE_REG; + case FST_GLB_TSADC_RST_ST: + case SND_GLB_TSADC_RST_ST: + return RST_CAUSE_THERMAL; + case FST_GLB_WDT_RST_ST: + case SND_GLB_WDT_RST_ST: + return RST_CAUSE_WDOG; + } + + return RST_CAUSE_UNKNOWN; +} -- 2.34.1