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[2a02:3100:a8e9:c501:f941:243b:87f6:e5a2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fcd1149e0sm198706585e9.13.2026.09.20.23.00.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 20 Sep 2026 23:00:22 -0700 (PDT) From: Karl Mehltretter To: Russell King , Dmitry Baryshkov , Sudeep Holla Cc: Karl Mehltretter , Pierre Gondois , Linus Walleij , Radu Rendec , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , linux-arm-kernel@lists.infradead.org, linux-rt-devel@lists.linux.dev, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v2 0/4] ARM: allocate the cacheinfo early to fix the PREEMPT_RT boot warning Date: Mon, 21 Sep 2026 08:00:09 +0200 Message-Id: <20260921-arm-cacheinfo-v2-5892c4531ad9-0@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: References: <20260912195552.76673-1-kmehltretter@gmail.com> Content-Type: text/plain; charset="utf-8" Precedence: bulk X-Mailing-List: linux-rt-devel@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series moves ARM cacheinfo allocation to the boot CPU to avoid sleeping-lock warnings during PREEMPT_RT secondary-CPU startup. It is rebased onto v7.3-rc1, cee9395acd8043be0644b25c34bfa86623f2b935. Patches 1-3 prepare for early allocation: bound cache-leaf writes, include external caches in the allocation size, and guard CLIDR reads on older CPUs. Patch 4 enables early allocation. Please take all four patches together for stable. Changes in v2: - Rebase from post-v7.3-rc2 mainline (5225b8eec4c9) onto v7.3-rc1 as Linus requested [1]. - Add Sebastian's Tested-by and links to the original patch posts. - Retest the full series on this base; results below. The four code diffs are unchanged. Fresh testing on this v7.3-rc1 base used GCC 15.2.0 and QEMU 10.2.1. Three full kernel builds and W=1 checks of cacheinfo.o/topology.o passed: multi_v7_defconfig with and without PREEMPT_RT, and an ARMv6+ARMv7 SMP PREEMPT_RT configuration for ARM11 MPCore. Seven boot checks passed: - virt, Cortex-A15, 2 and 4 CPUs, with and without PREEMPT_RT; - vexpress-a9, Cortex-A9 with external PL310 L2, 4 CPUs, RT and non-RT; - realview-eb-mpcore, ARM11 MPCore, 4 CPUs, PREEMPT_RT. With DEBUG_ATOMIC_SLEEP enabled, the RT boot warning was absent. CPU1 offline/online succeeded in every run, with identical cache sysfs output before and after. ARM11 exposed no cache leaves, as expected. RT and non-RT cache output also matched on each ARMv7 machine. All four stable patch IDs match v1. Earlier testing of these same diffs also covered DT cache-description corner cases. On September 12, the full series passed on a Raspberry Pi 400 with a 32-bit PREEMPT_RT 7.2.6-rc1 kernel: the boot warning was absent and all 12 cache sysfs entries matched the baseline. CPU hotplug was unavailable there. That hardware test and the DT corner-case tests were not repeated on this rebased tree. v1: https://lore.kernel.org/r/20260912195552.76673-1-kmehltretter@gmail.com/ [1] https://lore.kernel.org/r/CAD++jL=7OSrPMax9GRj3D7ehjmmG2uMyws53F8U0x7YGx+RNOQ@mail.gmail.com/ Karl Mehltretter (4): ARM: cacheinfo: avoid out-of-bounds write in populate_cache_leaves() ARM: cacheinfo: count external caches in early_cache_level() ARM: cacheinfo: guard the CLIDR read in populate_cache_leaves() ARM: topology: allocate the cacheinfo early on the boot CPU arch/arm/kernel/cacheinfo.c | 49 +++++++++++++++++++++++---------------------- arch/arm/kernel/topology.c | 13 ++++++++++++ 2 files changed, 38 insertions(+), 24 deletions(-) base-commit: cee9395acd8043be0644b25c34bfa86623f2b935